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AM49DL640BG40IT

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型号: AM49DL640BG40IT
PDF文件:
  • AM49DL640BG40IT PDF文件
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功能描述: Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
PDF文件大小: 1103.02 Kbytes
PDF页数: 共62页
制造商: SPANSION[SPANSION]
制造商LOGO: SPANSION[SPANSION] LOGO
制造商网址: http://www.spansion.com
捡单宝AM49DL640BG40IT
PDF页面索引
120%
March 8, 2002 Am49DL640BG 31
PRELIMINARY
RY/BY#: Ready/Busy#
The RY/BY# is a dedicated, open-drain output pin
which indicates whether an Embedded Algorithm is in
progress or complet e. T he RY /BY# status is valid after
the rising edge of the final WE# pulse in the command
sequence. Since RY/BY# is an open-drain output , sev-
eral RY/BY# pins c an be tied together in parallel with a
pull-up resistor to V
CC
.
If the output is low (Bus y), the device is actively eras -
ing or program ming. (This includes programming in
the Erase Suspend mode.) If the output is high
(Rea dy) , th e dev ice is in the rea d mode , th e sta ndby
mode, or one of the banks is in the erase-sus-
pend-read mode.
Table 13 shows the outputs for RY/BY#.
DQ6: Toggle Bit I
Togg le B it I on DQ6 in dica tes w het her an E mb edde d
Program or Erase algorithm is in progress or com-
plete, or w hether th e device has entered the Eras e
Suspend mode. Toggle Bit I may be read at any ad-
dress, and is vali d afte r the r ising edge o f the fina l
WE# pulse in the command sequence (prior to the
program or er ase operat ion), and during the sector
erase time-out .
During an Embedded Program or Erase algorithm op-
eration, successive r ead cycles to any address cause
DQ6 to toggle. The system may use either OE# or
CE#f to control the read cycles. When the operation is
complet e, DQ6 stops toggling.
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6 tog-
gles for approximately 100 µs, then returns to reading
array data. If not all selected sectors are protected, the
Embedded Erase algorithm erases the unpr otected
sectors, and ignores the selected sectors that are pro-
tected.
The system can use DQ 6 and DQ2 t ogether to det er-
mine whether a sector is actively erasing or is
erase-suspended. When the device is actively erasing
(that is, the Embedded Erase algorithm is in progress),
DQ6 togg les. Whe n the device enters the E rase Sus -
pend mode, DQ6 stops toggling. However, the system
must also use DQ2 to determin e which s ectors are
erasing or erase-suspended. Alternatively, the system
can use DQ7 (see the subsection on DQ7: Data# Poll-
ing).
If a program address falls within a protected sector,
DQ6 toggles for approximately 1 µs af ter the program
command sequence is written, then returns to reading
array data.
DQ 6 al so to ggl es d urin g th e er ase-s usp end- prog ram
mod e, and stops toggling once the Embedde d Pro-
gram algorithm is complete.
Table 13 s hows the outputs for Toggle Bit I on DQ6.
Figure 6 shows the toggle bit algorithm. Figure 23 in
the Flash AC Characteristics section shows th e tog-
gle bit timing d iagrams. Figure 24 shows the differ-
enc es be twe en DQ2 an d DQ6 i n g raphi cal for m. S ee
also the subsection on DQ2: Toggle Bit II.
Figure 6. Toggle B it A lgor it h m
START
No
Yes
Yes
DQ5 = 1?
No
Yes
Toggle Bit
= Toggle?
No
Program/Erase
Operation Not
Complete, Write
Reset Command
Program/Erase
Operation Complete
Toggle Bit
= Toggle?
Read Byte Twice
(DQ7DQ0)
Address = VA
Read Byte
(DQ7DQ0)
Address =VA
Read Byte
(DQ7DQ0)
Address =VA
Note: The system should recheck the toggle bit even if DQ5
= 1 because the toggle bit ma y stop toggling as DQ5
changes to 1. See the subsections on DQ6 and DQ2 for
more information.
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