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AM49DL640BG40IT

AM49DL640BG40IT首页预览图
型号: AM49DL640BG40IT
PDF文件:
  • AM49DL640BG40IT PDF文件
  • AM49DL640BG40IT PDF在线浏览
功能描述: Stacked Multi-Chip Package (MCP) Flash Memory and SRAM
PDF文件大小: 1103.02 Kbytes
PDF页数: 共62页
制造商: SPANSION[SPANSION]
制造商LOGO: SPANSION[SPANSION] LOGO
制造商网址: http://www.spansion.com
捡单宝AM49DL640BG40IT
PDF页面索引
120%
March 8, 2002 Am49DL640BG 13
PRELIMINARY
may be initi ated for s imultan eou s ope ration with zero
latency. I
CC6
f and I
CC7
f in the table represe nt the cur-
rent specifications for read-while-program and
read-while-erase, respectively.
Standby Mode
When the system is not reading or writing to the de-
vice, it can place the device in the standby mode. In
this m ode, cur rent cons umption i s greatly reduce d,
and the outputs are placed in the high impedance
state, independent of the OE# input.
The device enters the CMOS standby mode when the
CE#f a nd R ESET# pins a re bot h hel d at V
CC
± 0.3 V.
(Note that this is a more restricted voltage ran ge than
V
IH
.) If CE#f and RESET# are held at V
IH
, but not
within V
CC
± 0.3 V, the device will be in the standby
mode, but the standby current will be greater. The de-
vice requires standard access time (t
CE
) for read ac-
cess when the device is in either of these standby
modes, before it is ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is complet ed.
I
CC3
f in the table represents the standby current spec-
ification.
Automatic Sleep Mode
The aut om atic sleep m ode m inim ize s Flash dev ic e en-
erg y con sumption. The device au tomaticall y enabl es
this mode when addresses remain stable for t
ACC
+
30 ns. The au tomatic sleep mode is in dependent of
the CE#f, W E#, and OE# control signals. Standard ad-
dress access timings provide new data when ad-
dresses are changed. While in sleep mode, output
data is latched and alwa ys available to the sy stem.
I
CC5
f in t he tabl e r epr es ents the automatic s leep mode
current spec ifi cation.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of re-
setting t he dev ice to reading array data. When t he RE -
SE T# pin is dr iven l ow fo r at le ast a p eriod of t
RP
, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/wr ite comm ands for the du ration of t he RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
SS
±0.3 V, the device
draws CMOS standby current (I
CC4
f). If RESET# is
held at V
IL
but not within V
SS
±0.3 V, th e standby cur-
rent will be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would t hus also reset t he Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RE SET# is asser ted duri ng a pr ogram or era se op-
eration, the RY/BY # pin remains a 0 (busy) unt il the
int ernal res et op eration is comp lete, wh ich r equires a
time of t
READY
(during Embedded Algorithms). The
system can thus monitor RY/BY# to determine
whether the reset operation is c omplete. If RESET# is
asserted when a program or eras e oper ation is not ex-
ecuting (R Y/BY# pin is 1), the reset operation is com-
pleted within a time of t
READ Y
(not during Embedded
Algorithms). The system can read data t
RH
after the
RESET# pin returns to V
IH
.
Refer to the pSRAM AC Characteristics tables for RE-
SE T# param eters a nd to Fi gure 15 for the timing dia -
gram.
Output Disable Mode
When the OE# in put is at V
IH
, out put from t he device is
disabled. The output pins are placed in the high
impedance state.
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