12 Am49DL640BG March 8, 2002
PRELIMINARY
FLASH DEVICE BUS OPERATIONS
Word/Byte Configurat ion
The CIOf pin controls whether t he devi ce data I /O pi ns
operate in the byte or word configuration. If the CIOf
pin is s et at lo gi c ‘1’, the device is in word configura-
tion, DQ15–DQ0 are acti ve and c ontrolled by C E#f
and OE#.
If the CIOf pin i s set a t lo gic ‘0’, the device is in byte
configuration, and only data I/O pins DQ7–DQ0 are
active and c ontrolle d by C E#f and OE #. Th e da ta I/O
pins DQ14–DQ8 are tri-stated, and the DQ15 pin is
used as an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array dat a from the o utputs, t he system must
drive the CE#f and OE# pins to V
IL
. CE#f is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at V
IH
. The CIOf pin determines
whether the device outputs array data in words or
bytes.
The inte rnal state machine is set fo r reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No com-
mand is necessary in this mode to obtain array data.
Standard microprocessor read cycles that assert valid
addresses on t he device address inputs produce valid
data on the device data outputs. Each bank remains
enabled for read access until the command register
contents are altered.
Refer to the Flash Read-Only Operations table f or tim-
ing specifications and to Figure 14 for the timing dia-
gram . I
CC1
in the DC Characteris tics table rep res ents
the active current specifi cation for r eading ar ray data.
W ritin g Commands/Command Seque nces
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sec tors of m emo ry) , th e sys te m mus t d rive WE # an d
CE#f to V
IL
, and O E# to V
IH
.
For program operations, the CIOf pin determines
whether the device accepts program data in bytes or
words. Refer to “Flash Device Bus Operations” for
more informa t ion.
The device features an Unlock Bypass mode to facil-
itate faster programming. Once a bank enters the Un-
lock Byp ass mode, only two write c ycles are require d
to program a word or byte, instead of four. The
“Byte/Word Program Command Sequence” section
has details on programming data to the device using
both standard and Unlock Bypass command se-
quences.
An erase operation can erase one sector, multiple sec-
tors, or the entire devic e. Table 3 indicates the addres s
space that each sector occupies. Similarly, a “sector
address” is the address bits required to uniquely select
a se ctor. The “F lash Command Definitions” section
has details on erasing a sector or the entire chip, or
suspending/resuming the erase operat ion.
The devic e addres s s pac e is divided int o f our banks. A
“bank address” is the addre ss bit s re quir ed to uniquely
select a bank.
I
CC2
in the DC Characteristics table represents the ac-
tive current specification for the writ e mode. The Flash
AC Characteristics section contains timing specifica-
tion tables and timing diagr ams for write operations.
Accelerated Program Operation
The device offers accelerated program operations
through the ACC function. This is one of two functions
provided by the WP#/ACC pin. This function is prima-
rily in tended t o allow faster manufac turing t hroughpu t
at the factory.
If th e system asser ts V
HH
on this pin, the device auto-
matically enters the aforement ion ed Unlock Bypass
mode, t emporarily unprotects any protected sectors,
and uses the higher voltage on the pin to reduce the
time required for program operations. The syst em
would use a two-cycle program command sequence
as required by the Unlock Bypas s mode. Removing
V
HH
from the WP #/ACC pin r eturns the device to n or-
mal operation. Note that V
HH
must not be asserted on
W P#/A CC for op erat ions ot her than a ccele rat ed pro -
gra mm ing, or dev ice da mage may resu lt. In ad dit ion,
the WP#/ACC pin must not be left floating or uncon-
nected; incons is tent behavior of the device may r es ult.
See “Write Protect (WP#)” on page 19 for related in-
formation.
Autoselect Functions
If the system writes the autoselect command se-
quence, the device enters the autoselect mode. The
system can then read autoselect codes from the inter-
nal register (which is separate from the memory array)
on DQ 15–DQ0. Standard read cycle timings apply in
this mode. Refer to the S ector/Sector Block Protection
and Unprotection and Autoselect Command Se-
quence sections for more information.
Simultaneous Read/Write Operations with
Zero Latency
This dev ice is capa ble of r eading data f rom one ba nk
of mem ory w hile prog ramming or eras ing in the o ther
bank of memory. An erase operation may also be sus-
pended to read from or program to another location
within the same bank (except the sector being
erased). Figure 21 shows how read and write cycles
