8 Am29LV800B
PRELIMINARY
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register . The command register itself
does not occupy any addressable memory location.
The register is compos ed of latches that store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the
inputs and control lev els t he y requ ire , and t he resulting
output. The following subsections describe each of
these operations in further detail.
Table 1. Am29LV800B Device Bus Operations
Legend:
L = Logic Low = V
IL
, H = Logic High = V
IH
, V
ID
= 12.0
±
0.5 V, X = Don’t Care, A
IN
= Address In, D
IN
= Data In, D
OUT
= Data Out
Notes:
1. Addresses are A18:A0 in word mode (BYTE# = V
IH
), A18:A-1 in byte mode (BYTE# = V
IL
).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector
Protection/Unprotection” section.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins DQ15–DQ0 oper ate in t he b y te or word c onfigur a-
tion. If the BYTE# pin is set at logic ‘1’, the device is in
word configur ation, DQ15–DQ0 are acti v e and c ontrol-
led by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configurat ion, and only data I/O pins DQ0–DQ7 are ac-
tive and controlled by CE# and OE#. The data I/O pins
DQ8–DQ14 are tri-stated, and the DQ15 pin is used as
an input for the LSB (A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
IL
. CE# is the power
control and selects the device. OE# is the output con-
trol and gates array data to the output pins. WE#
should remain at V
IH
. The BYTE# pin determines
whether the device outputs array data in words or
bytes.
The internal state machine is set for reading array
data upon de vic e po wer-up, or aft er a hardw are reset .
This ensures that no spur ious alteration of the me m-
ory content occurs during the power transition. No
command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that as-
sert v alid addresses on th e device addres s input s pro-
duce valid data on the device data outputs. The
de vice remains enabled f or read access unt il the com-
mand register contents are altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to Figure 13 for the timing diagram. I
CC1
in
the DC Characteristics table represents the active cur-
rent specification for reading array data.
Operation CE# OE# WE# RESET#
Addresses
(Note 1)
DQ0–
DQ7
DQ8–DQ15
BYTE#
= V
IH
BYTE#
= V
IL
Read L L H H A
IN
D
OUT
D
OUT
DQ8–DQ14 = High-Z,
DQ15 = A-1
Write L H L H A
IN
D
IN
D
IN
Standby
V
CC
±
0.3 V
XX
V
CC
±
0.3 V
X High-Z High-Z High-Z
Output Disable L H H H X High-Z High-Z High-Z
Reset X X X L X High-Z High-Z High-Z
Sector Protect (Note 2) L H L V
ID
Sector Ad dre ss,
A6 = L, A1 = H,
A0 = L
D
IN
XX
Sector Unp rot ect (Note 2) L H L V
ID
Sector Ad dre ss,
A6 = H, A1 = H,
A0 = L
D
IN
XX
Temporary Sector Unprotect X X X V
ID
A
IN
D
IN
D
IN
High-Z
