• 当前位置:
  • 首页
  • >
  • PDF资料
  • >
  • AM29LV800BT90WBCB PDF文件及第19页内容在线浏览

AM29LV800BT90WBCB

AM29LV800BT90WBCB首页预览图
型号: AM29LV800BT90WBCB
PDF文件:
  • AM29LV800BT90WBCB PDF文件
  • AM29LV800BT90WBCB PDF在线浏览
功能描述: 8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory
PDF文件大小: 569.02 Kbytes
PDF页数: 共42页
制造商: AMD[Advanced Micro Devices]
制造商LOGO: AMD[Advanced Micro Devices] LOGO
制造商网址: http://www.amd.com
捡单宝AM29LV800BT90WBCB
PDF页面索引
120%
Am29LV800B 19
PRELIMINARY
WRITE OPERATION STATUS
The device provides several bits to determine the sta-
tus of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7,
and R Y/BY# . Tab le 6 and the follo wing subsections de-
scribe the functions of these bits. DQ7, RY/BY#, and
DQ6 each offer a method for determining whether a
program or erase operation is complete or in progress.
These three bits are discussed first.
DQ7: Data# Polling
The Data# P olling bit, DQ7, indicates to the host system
whether an Embedded Algorithm is in progress or com-
pleted, or whether the device is in Erase Suspend.
Data# Polling is valid after the rising edge of the final
WE# pulse in the program or erase command se-
quence.
During the Embedded Program algorithm, the device
outputs on DQ7 the complement of the datum pro-
grammed to DQ7. This DQ7 status also applies to pro-
gramming during Erase Suspend. When the
Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7. The system
must provide the program address to read valid status
information on DQ7. If a program address falls within a
protected sector, Data# P olling on DQ7 is acti ve f or ap-
proximately 1 µs, then the device returns to reading
array data.
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7. When t he Embedded Erase al-
gorithm is complete, or if the device enters the Erase
Suspend mode, Data# Polling produces a “1” on DQ7.
This is analogous t o the complement/true datum output
described for the Embedded Program algorithm: the
erase function changes all the bits in a sector to “1”;
prior to this, the device outputs the “complement,” or
“0.” The system must provide an address within any of
the sectors selected for erasure to read valid status in-
formation on DQ7.
After an er ase command sequence is written, if all sec-
tors selected for erasing are protected, Data# Polling
on DQ7 is active f or appro ximately 100 µs , the n the de-
vice returns to reading array data. If not all selected
sectors are protected, the Embedded Erase algorithm
erases the unprotected sectors, and ignores the se-
lected sectors that are protected.
When the system detects DQ7 has changed from the
complement to true data, it can read valid dat a at DQ7–
DQ0 on the
f ollowing
read cycles . This is because DQ7
may change asynchronously with DQ0–DQ6 while
Output Enable (OE#) is as serted low. Figure 19, Data#
Polling Timings (During Embedded Algorithms), in the
“AC Characteristics” section illustrates this.
Table 6 shows the outputs for Data# Polling on DQ7.
Figure 5 shows the Data# Polling algorithm.
DQ7 = Data?
Yes
No
No
DQ5 = 1?
No
Yes
Yes
FAIL
PASS
Read DQ7–DQ0
Addr = VA
Read DQ7–DQ0
Addr = VA
DQ7 = Data?
START
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. DQ7 should be rechecked even if DQ5 = “1” because
DQ7 may change simultaneously with DQ5.
21490E-9
Figure 5. Data# Polling Algorithm
购买、咨询产品请填写询价信息:(3分钟左右您将得到回复)
询价型号*数量*批号封装品牌其它要求
删除
删除
删除
删除
删除
增加行数
  •  公司名:
  • *联系人:
  • *邮箱:
  • *电话:
  •  QQ:
  •  微信:

  • 关注官方微信

  • 联系我们
  • 电话:13714778017
  • 周一至周六:9:00-:18:00
  • 在线客服:

天天IC网由深圳市四方好讯科技有限公司独家运营

天天IC网 ( www.ttic.cc ) 版权所有©2014-2023 粤ICP备15059004号

因腾讯功能限制,可能无法唤起QQ临时会话,(点此复制QQ,添加好友),建议您使用TT在线询价。

继续唤起QQ 打开TT询价