PRELIMINARY
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to hel p you e val uate this product. A MD reserves the right to change or discontin ue work on this proposed
product without notice.
Publicati on# 21490 Rev: E Amendment/+1
Issue Date: March 1998
Refer to AMD’s Website (www.amd.com) for the latest information.
Am29LV800B
8 Megabit (1 M x 8-Bit/512 K x 16-Bit)
CMOS 3.0 Vo lt -only Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
■ Single power supply operation
— Full v olt age r ange: 2.7 to 3.6 volt read and write
operations for battery-powered applications
— Regulated voltage range: 3.0 to 3.6 volt read
and write operations and for compatibility with
high performance 3.3 volt microprocessors
■ Manufact ured on 0.35 µm process technology
— Compatible with 0.5 µm Am29LV800 device
■ High performan ce
— Full voltage r ange: access times as fast as 80 ns
— Regulated voltage range: access times as fast
as 70 ns
■ Ultra low power consumption (typical values at
5 MHz)
— 200 nA Automatic Sleep mode current
— 200 nA standby mode current
— 7 mA read current
— 15 mA program/erase current
■ Flexible sector architecture
— O ne 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and
fifteen 64 Kbyte sectors (byte mode)
— One 8 Kword, two 4 Kword, one 16 Kword, and
fifteen 32 Kword sectors (word mode)
— Supports full chip erase
— Sector Prot ection features:
A hardware method of locking a sector to
prevent any program or erase oper ations within
that sector
Sectors can be locked in-system or via
programming equipment
Temporary Sector Unprotect feature allows code
changes in prev iously locked sectors
■ Unlock Bypass Program Comm an d
— Reduces overall programming time when
issuing multiple program command sequences
■ Top or bottom boot block configurations
available
■ Embedded Al gorithms
— Embedded Erase algorithm automatically
preprogr ams and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically
writes and verifies data at specif ied addresses
■ Minimum 1,000,000 write cycle guarantee per
sector
■ Package option
— 48-ball FBGA
— 48-pin TSOP
— 44-pin SO
■ Compatibility with JEDEC standards
— Pinout and software compatible with single-
power supply Flash
— Superior inadvertent write protection
■ Data# Polling and toggle bits
— P rovides a software method of detecting
program or erase operation completion
■ Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting
program or erase cycle completion
■ Erase Suspend/Erase Resume
— Suspends an erase oper ation to read data from,
or progr am data to, a sector that is not being
erased, then res umes the erase operation
■ Hardware reset pin (RESET#)
— Hardw are method to reset the de vice t o reading
array data
