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AM29F002T-90ECB

AM29F002T-90ECB首页预览图
型号: AM29F002T-90ECB
PDF文件:
  • AM29F002T-90ECB PDF文件
  • AM29F002T-90ECB PDF在线浏览
功能描述: 2 Megabit (256 K x 8-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory
PDF文件大小: 436.41 Kbytes
PDF页数: 共37页
制造商: AMD[Advanced Micro Devices]
制造商LOGO: AMD[Advanced Micro Devices] LOGO
制造商网址: http://www.amd.com
捡单宝AM29F002T-90ECB
PDF页面索引
120%
8 Am29F002/Am29F002N
PRELIMINARY
Status” for more information, and to each AC Charac-
teristics section for timing diagrams.
Standby Mode
When the system is not reading or writing to t he device ,
it can place the device in the standby mode. In this
mode, current co nsumption is g reat ly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input.
The de vice enters the CMOS standb y mode when CE#
and RESET# pins (CE# only on the Am29F002N) are
both held at V
CC
± 0.5 V. (Note that this is a more re-
stricted voltage range than V
IH
.) The device enters the
TTL standb y mode when CE# and RESET# pins (CE#
only on the Am29F002N) ar e both held at V
IH
. The de-
vice requires standard access time (t
CE
) for read ac-
cess when the device is in either of these standby
modes, before it is ready to read data.
The device also enters the standby mode when the RE-
SET# pin is dr iven low. Refer to the next section, “RE-
SET#: Hardware Reset Pin”.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
In the DC Characteristics tables, I
CC3
represents the
standby current specification.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
I
CC3
in the DC Characteristics tables represents the
standby current specification.
RESET#: Hardware Reset Pin
Note: The RESET# pin is not available on the
Am29F002N.
The RESET# pin p rovides a hard ware method of reset-
ting the device t o readin g arr a y data. When the s ystem
drives the RESET# pin low for at least a period of t
RP
,
the device immediately terminates any operation in
progress, tristates all data output pins, and ignores all
read/write attempts for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the de vice is ready
to accept another command sequence, to ensure data
integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
IL
, the device enters
the TTL standby mode; if RESET# is held at V
SS
±
0.5 V, the device ent ers the CMOS standby mode.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
Refer to the AC Characteristics tables for RESET# pa-
rameters and timing diagram.
Output Disable Mode
When the OE# input is at V
IH
, output from the device is
disabled. The output pins are plac ed in the h igh imped-
ance state.
Table 2. Am29F002/Am29F002N Top Boot Block Sector Address Table
Sector A17 A16 A15 A14 A13
Sector Size
(Kbytes)
Address Range
(in hexadecimal )
SA0 0 0 X X X 64 00000h– 0F FFF h
SA1 0 1 X X X 64 10000h– 1F FFF h
SA2 1 0 X X X 64 20000h– 2F FFF h
SA3 1 1 0 X X 32 30000h–37FFF h
SA4 1 1 1 0 0 8 38000h– 39 FFF h
SA5 1 1 1 0 1 8 3A000h– 3B FF Fh
SA6 1 1 1 1 X 16 3C000h–3FFFF h
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