2 Am29F002/Am29F002N
PRELIMINARY
GENERAL DESCRIPTION
The Am29F002 Family consists of 2 Mbit, 5.0 volt-only
Flash memory devices organized as 262,144 bytes.
The Am29F002 offers the RESET# function, the
Am29F002N does not. The data appears on DQ7–
DQ0. The device is offered in 32-pin PLCC, 32-pin
TSOP, and 32-pin PDIP packages. This device is
designed to be programmed in-system with the
standard system 5.0 volt V
CC
supply. No V
PP
is
required for write or erase operations. The device can
also be programmed in standard EPROM program-
mers.
The standard device offers access times of 55, 70, 90,
and 120 ns, allowing high speed microprocessors to
operate wit hout wait st ates. To eliminate bus c ontention
the device has separate chip enable (CE#), write
enable ( WE#) and output enab le (OE#) controls.
The de vice requires only a single 5.0 vol t po wer sup-
pl y for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.
The de vice is entirely command set compatib le with the
JEDEC single-power-supply Flash standard. Com-
mands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as input to an internal state-machine that
controls the erase and programming circuitry. Write
cycles also internally latch addresses and data needed
for the programming and erase operations. Reading
data out of the device is similar to reading from other
Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the Embedded
Program algorithm—an internal algorithm that auto-
matically times the program pulse widths and verifies
proper cell margin.
Device erasure occurs by executing the erase com-
mand sequence. This initiates the Embedded Erase
algorithm—an internal algorithm that automatically
preprograms t he arra y (if it is not already progr ammed)
bef ore ex ecuting the e rase operation. During er ase, the
device automatically times the erase pulse widths and
verifies proper cell margin.
The host system can detect whether a program or
erase operation is complete by reading the DQ7 (Data#
Polling) and DQ6 (toggle) status bits. After a progr am
or erase cycle has been completed, the de vice is ready
to read array data or accept another command.
The sector erase ar chitecture allo ws memo ry se ctors
to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achie v ed via prog ramming equipment.
The Erase Suspend feature enables the user to put
erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for
erasure . True bac kgro und eras e can thus be achiev ed.
The hardware RESET# pin terminates any operation
in progress and resets the internal state machine to
reading arr a y data. The RESET# pin ma y be tied to the
system reset circuitr y. A system reset would thus also
reset the device, enabling the system microprocessor
to read the boot-up firmware from the Flash memor y.
(This feature is not available on the Am29F002N.)
The system can place the device into the standby
mode. Power consumption is greatly reduced in this
mode.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the
highest levels of quality, reliability and cost effective-
ness. The device electrically erases all bits within
a sector simultaneously via Fowler-Nordheim tun-
neling. The data is programmed using hot electron
injection.