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AM29F002T-90ECB

AM29F002T-90ECB首页预览图
型号: AM29F002T-90ECB
PDF文件:
  • AM29F002T-90ECB PDF文件
  • AM29F002T-90ECB PDF在线浏览
功能描述: 2 Megabit (256 K x 8-Bit) CMOS 5.0 Volt-only Boot Sector Flash Memory
PDF文件大小: 436.41 Kbytes
PDF页数: 共37页
制造商: AMD[Advanced Micro Devices]
制造商LOGO: AMD[Advanced Micro Devices] LOGO
制造商网址: http://www.amd.com
捡单宝AM29F002T-90ECB
PDF页面索引
120%
10 Am29F002/Am29F002N
PRELIMINARY
Contact an AMD representat ive to obtain a copy of the
appropriate document.
The device is shipped with all sectors unprotected.
AMD offers the option of programming and protecting
sectors at its factory prior to shipping the device
through AMDs ExpressFlash™ Service. Contact an
AMD representative for details.
It is possib le to determine whether a sector is protected
or unprotected. See “Autoselect Mode” for details.
Temporary Sector Unprotect
Note: This feature requites the RESET# pin and is
therefore not available on the Am29F002N.
This feature allows temporary unprotection of previ-
ously protected sectors to change data in-system.
The Sector Unpr otect mode is activ at ed by setting the
RESET# pin to V
ID
. During this mode, formerly pro-
tected sectors can be programmed or erased by se-
lecting the sector addresses. Once V
ID
is removed
from the RESET# pin, all the previously protected
sectors are prot ected again. Figure 1 shows the algo-
rithm, and the Temporary Sector Unprotect diagram
shows the timing waveforms, for this feature.
Figure 1. Temporary Sector Unpr otect Operation
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
against inadvertent writes (refer to the Command Defi-
nitions table). In addition, the following hardware data
protection meas ures pre vent a ccidental eras ure or pro-
gramming, which might otherwise be caused by spuri-
ous system level signals during V
CC
power-up and
power-down transitions, or from system noise.
Low V
CC
Write Inhibit
When V
CC
is less than V
LKO
, the device does not ac-
cept any write cycles. This protects data during V
CC
power-up and power-do wn. The command register and
all internal program/er ase circuits are disabled, and the
dev ice resets . Subsequent writes are ignored until V
CC
is greater than V
LKO
. The system must provide the
proper signals to the control pins to prevent uninten-
tional writes when V
CC
is greater than V
LKO
.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
Logical In hibit
Write cycles are inhibited by holding any one of OE# =
V
IL
, CE# = V
IH
or WE# = V
IH
. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = V
IL
and OE# = V
IH
during pow er up, the
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on po wer-up.
START
Perform Erase or
Program Operations
RESET# = V
IH
Temporary Sector
Unprotect
Completed (Note 2)
RESET# = V
ID
(Note 1)
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once
again.
20818C-4
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