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AM29DL320GB50PCIN

AM29DL320GB50PCIN首页预览图
型号: AM29DL320GB50PCIN
PDF文件:
  • AM29DL320GB50PCIN PDF文件
  • AM29DL320GB50PCIN PDF在线浏览
功能描述: 32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory
PDF文件大小: 1185.79 Kbytes
PDF页数: 共58页
制造商: AMD[Advanced Micro Devices]
制造商LOGO: AMD[Advanced Micro Devices] LOGO
制造商网址: http://www.amd.com
捡单宝AM29DL320GB50PCIN
PDF页面索引
120%
2 Am29DL320G
GENERAL DESCRIPTION
The Am29DL320G is a 32 megabit, 3.0 volt-only flash
memory device, organized as 2,097,152 words of 16
bits each or 4,194,304 bytes of 8 bits each. Word
mode data ap pears on DQ15–DQ0; byte mode data
appears on DQ7–DQ0. The device is designed to be
programmed in-system with the standard 3.0 volt V
CC
supply, and can also be programmed in standard
EPROM programmers.
The device is available with an access time of 70, 90,
or 120 ns. The devices are offered in 48-pin TSOP,
48-ball or 63-ball FBGA packages, and 64-ball For ti-
fied BGA. Standard control pins—chip enable (CE#),
write enable (WE#), and output enable (OE#)—control
normal read and write operations, and avoid bus con-
tention issues.
The de vice require s only a single 3.0 volt power s up-
ply for both read and write functions. Internally gener-
ated and regulated voltages are provided for the
program and erase operations.
Simultaneous Rea d/Write Operations with
Zero Latency
The Simultaneous Read/Wr ite architecture provides
simultaneous operation by dividing the memor y
space into f our banks , tw o 4 Mb banks with small and
large sectors, and two 12 Mb banks of large sectors.
Sector addresses are fixed, system software can be
used to form user-defined bank groups.
During an Erase/Program operation, any of the three
non-busy banks may be read from. Note that only two
banks can operate simultaneously. The device allows
a host system to program or erase in one bank, then
immediately and simultaneously read from the other
bank, with zero latency. This releases the system from
waiting for the completion of program or erase
operations.
The Am29DL320G can be organized as either a top or
bottom boot sector configuration.
Am29DL320G Features
The
SecSi
TM
(Secured Silicon) Sector
is an 256 byte
ex tra sector capable of being permanently locked by
AMD or customers. The SecSi Indicator Bit (DQ7) is
permanently set to a 1 if the par t is factory locked,
and set to a 0 if customer lockable. This way, cus-
tomer lockable par ts can never be used to replac e a
factor y locked par t. Note that some previous AMD
32 Mbit Am29DL32x devices had a larger SecSi
Sector. Factor y locke d par ts provide several options.
The SecSi Sector may store a secure, random 16 byte
ESN (Electronic Serial Number), customer code (pro-
grammed through AMD’s ExpressFlash service), or
both.
DMS (Data Management Software) allows systems
to remove EEPROM devices. by simplifying system
software: DMS performs all functions necessary to
modify data in file structures, instead of using sin-
gle-byte modifications. To write or update a par ticular
piece of data (a phon e number or configuration data,
for example), the user only needs to state which piece
of data is to be updated, and where the updated data
is located in the system. Th is is an advantag e com-
pared to systems where user-written software must
keep track of the old data locatio n, status, logical to
physical translation of the data onto the Flash memory
device (or memory devices), and more. Using DMS,
user-written software does not need to interface with
the Flash memory directly. Instead, the user's softw are
accesses the Flash memor y by calling one of only six
functions. AMD prov ides this software to simplify sys-
tem design and software integration efforts.
The device offers complete compatibility with the
JEDEC single-power-supply Flash command set
standard. Commands are written to the command
register using standard micro processor write timing s.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
The host system can detect whether a program or
erase operation is complete by using the device sta-
tus bits: RY/BY# pin, DQ7 (Data# Polling) and
DQ6/DQ2 (toggle bits). After a program or erase cycle
has been completed, the device automatically returns
to the read mode.
The sector erase architecture allows memor y sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The dev ice is fully
erased when shipped from the factory.
Hardware data protection measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The hardware sector
protection feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved in-system or via program-
ming equipment.
The device offers two power-saving features. When
addresses have be en stable for a specified amo unt of
time, the device enters the automatic sleep mode.
The system can also place the device into the
standby mode. Power consumption is greatly re-
duced in both modes.
Bank Megabits Sector S izes
Bank 1 4 Mb
Eight 8 Kbyte/4 Kword,
Seven 64 Kbyte/32 Kword
Bank 2 12 Mb Twenty-four 64 Kbyte/32 Kword
Bank 3 12 Mb Twenty-four 64 Kbyte/32 Kword
Bank 4 4 Mb Eight 64 Kb yte/32 Kword
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