Am29DL320G 31
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whe ther a par ticular sector is actively erasing
(that is, th e Embedded Er ase algorithm is in progre ss),
or whether that se ctor is erase-suspended. Tog gle Bit
II is v alid after the rising edge of the final WE# pulse in
the command sequence.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system may use either OE# or CE# to con-
trol the read cycles.) But DQ2 cannot distinguish
whether the se ctor is actively erasing or is erase-s us-
pended. DQ6, by comparison, indicates whether the
device is actively erasing , or is in Erase Suspend, but
cannot distinguish which sectors are selected for era-
sure. Thus, both status bits are required for sector and
mode infor mation. Refer to Table 14 to compare out-
puts for DQ2 and DQ6.
Figure 7 shows the toggle bit algorithm in flowchar t
for m, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the DQ6: Toggle Bit I subsection.
Figure 23 shows the toggle bit timing diagram. Figure
24 shows the differences between DQ2 and DQ 6 in
graphical form.
Reading Toggle Bits DQ6/DQ2
Refer to Figure 7 for the following discussion. When-
ever the system initially begins reading toggle bit sta-
tus, it must read DQ7–DQ0 at least twice in a row to
determine whether a toggle bit is toggling. Typically,
the system would note and store the value of the tog-
gle bit after the first read. After the second read , the
system would compare the new value of the toggle bit
with the first. If the toggle bit is not toggling, the device
has completed the progra m or erase operation. The
system can read array data on DQ7–DQ0 on the fol-
lowing read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the sys-
tem also should note whether the value of DQ5 is high
(see the section on DQ5). If it is, the system should
then determine again whether the toggle bit is tog-
gling, since the toggle bit may have stopped toggling
just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or er ase oper ation. If it is st ill toggling, the de-
vice did not completed the operation successfully, and
the system must write the reset command to return to
reading array data.
The remaining scenario is that the system initially de-
term ines that the toggle bit is toggling and DQ5 has
not gone high. Th e system may co ntinu e to monitor
the toggle bit an d DQ5 through successive read cy-
cles, determining the sta tus as describ ed in the previ-
ous paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must star t
at the beginning of the algorithm when it returns to de-
termine the status of the operation (top of Figure 7).
DQ5: Exceeded Timing Limits
DQ5 indicates whe th er th e program or erase time has
e xceeded a specified internal pulse count limit. Under these
conditions DQ5 produces a “1,” indicating that the progr am
or erase cycle was not successfully completed.
The de vice may output a “1” on DQ5 if the system tries
to program a “1” to a location that was previously pro-
grammed to “0.” Only an erase operation can
change a “0” back to a “1.” Under this condition, the
device halts the operation, and when the timing limit
has been exceeded, DQ5 produces a “1.”
Under both these conditions, the system must write
the reset command to retur n to the read mode (or to
the erase-suspend-read mode if a bank was previ-
ously in the erase-suspend-program mode).
DQ3: Sector Erase Timer
After writing a sector erase command sequence, the
system may read DQ3 to determine whether or not
erasure has begun. (The sector e rase timer does not
apply to the chip erase command.) If additional
sectors are se lected for erasure, the entire tim e-out
also applies after each additional sector erase com-
mand. When the time-out period is complete, DQ3
sw itches from a “0” to a “1.” If the time between addi-
tional sector erase commands from the system can be
assumed to be less than 50 µs, the system need not
monitor DQ3. Se e also the Sector Erase Co mmand
Sequence section.
After the sector erase command is written, the system
should read the status of DQ7 (Data# Polling) or DQ6
(Toggle Bit I) to ensure that the device h as accepted
the command sequence , and then rea d DQ3. If DQ3 is
“1,” the Embedded Erase algorithm has begun; all fur-
ther commands (except Erase Suspend) are ignored
until the erase operation is complete. If DQ3 is “0,” the
device will accept additional sector erase commands.
To ensure the command has been accepted, the sys-
tem software should check the status of DQ3 prior to
and following each subsequent sector erase com-
mand. If DQ3 is high on the second status check, the
last command might not have been accepted.
Table 14 shows the status of DQ3 relative to the other
status bits.
