Am29DL320G 11
dress access timings provide new data when ad-
dresses are changed. While in sleep mode, output
data is latched and always available to the system.
I
CC5
in the DC Characteristics table represents the
automatic sleep mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin p rov ides a hardware method of re-
setting the device to reading array data. When the RE-
SET# pin is dr iven low for at least a per iod of t
RP
, the
device immediately terminates any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state ma-
chine to reading array data. The operation that was in-
terrupted should be reinitiated once the device is
ready to accept another command sequence, to en-
sure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
SS
±0.3 V, the device
dra ws CMOS standb y c urrent (I
CC4
). If RESET# is held
at V
IL
but not within V
SS
±0.3 V, the standby current will
be greater.
The RESET# pin may b e tied to the system reset cir-
cuitr y. A system r eset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase op-
eration, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of t
READY
(during Embedded Algorithms). The sys-
tem can thus monitor RY/BY# to deter mine whether
the reset operation is c omplete . If R ESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of t
READY
(not dur ing Embedded Algo-
rithms). The system can read data t
RH
after the RE-
SET# pin returns to V
IH
.
I
CC4
in the DC Characteristics table represents the
reset current. Also refer to AC Characteristics tables
f or RESET# ti ming parameter s and to Figure 15 for the
timing diagram.
Output Disable Mode
When the OE# input is at V
IH
, output from the de vice is
disabled. The output pins are placed in the high
impedance state.
