Am28F256A 7
PIN DESCRIPTION
A0–A14
Address Inputs for memory locations. Internal latches
hold addresses dur ing write cycles.
CE# (E#)
Chip Enab le activ e low input activ ates the chip’ s control
logic and input buffers. Chip Enable high will deselect
the device and operates the chip in stand-by mode.
DQ0-DQ7
Data Inputs during memory write cycles. Internal
latches hold data during write cycles. Data Outputs
during memory read cycles.
NC
No Connect-corresponding pin is not connected
internally to the die.
OE# (G#)
Output Enab le acti ve low input gates the outp uts of the
device through the data buffers during memory read
cycles. Output Enable is high during command
sequencing and program/erase operations.
V
CC
P ow er supply f or de vice operat ion. (5.0 V ± 5% or 10%)
V
PP
Program voltage input. V
PP
must be at high voltage in
order to write to the command register. The command
register controls all f unctions required to alter th e mem-
ory array contents . Memory contents cannot be altered
when V
PP
≤ V
CC
+2 V.
V
SS
Ground.
WE# (W)
Write Enable active low input controls the write function
of the command register to the memory arra y . The t arget
address is latched on the falling ed ge of the Write En-
able pulse and the appropriate data is latched on the ris-
ing edge o f the pulse. Write Enable high inhibits wr iting
to the device.
