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AM28F256A-120FC

AM28F256A-120FC首页预览图
型号: AM28F256A-120FC
PDF文件:
  • AM28F256A-120FC PDF文件
  • AM28F256A-120FC PDF在线浏览
功能描述: 256 Kilobit (32 K x 8-Bit) CMOS 12.0 Volt, Bulk Erase Flash Memory with Embedded Algorithms
PDF文件大小: 456.67 Kbytes
PDF页数: 共35页
制造商: AMD[Advanced Micro Devices]
制造商LOGO: AMD[Advanced Micro Devices] LOGO
制造商网址: http://www.amd.com
捡单宝AM28F256A-120FC
PDF页面索引
120%
Am28F256A 17
DQ5
Exceeded Timing Limits
DQ5 will indicate if the program or erase time has
exceeded the specified limits. This is a failure condi-
tion and the device may not be used again (internal
pulse count exceeded). Under these conditions DQ5
will produce a “1.” The pro gram or er ase cycle was not
successfully completed. Data# Polling is the only op-
eratin g function of the de vice under th is condition. The
CE# circuit will partially power down the device under
these conditions (to approximately 2 mA). The OE#
and WE# pins will control the output disable functions
as described in the Command Definitions table in the
corresponding device data sheet.
Parallel Device Erasure
The Embedded Erase algorithm greatly simplifies par-
allel dev ice erasure. Since th e erase process is internal
to the dev ic e, a single eras e command can be given to
multiple de vices concurrently. By implementing a paral-
lel erase algorithm, total erase ti me may be minimized.
Note that the Flash memories may erase at different
rates. If this is the case, when a device is completely
erased, us e a mask ing code to prev ent further erasure
(ov er-erasure). The other de vices will continue t o erase
until verified. The masking code applied could be the
read command (00h).
Power-Up/Power-Down Sequence
The device powers-up in the Read only mode. Power
supply sequencing is not required. Note that if V
CC
1.0 Volt, the voltage difference between V
PP
and V
CC
should not exceed 10.0 Volts. Also, the device has a
rise V
PP
rise time and fall time specification of 500 ns
minimum.
Reset Command
The Reset command initializes the Flash memory de-
vice to the Read mode . In addition, it als o provides the
user with a safe method to abort any device operation
(including program or erase).
The Reset must be written two consecutive times after
the Setup Program command (10h or 50h). This will
reset the de vice to the Read mode.
Following any other Flash command, write the Reset
command once to the device. This wi ll safely abort any
prev ious operation and init ialize the device to t he Read
mode.
The Setup Program command (10h or 50h) is the only
command that requires a two-sequence reset cycle. The
first Reset command is interpreted as program data.
However , FFh data is considered as null data during pro-
gramming operations (memory cells are only pro-
grammed from a logical “1" to “0"). The second Reset
command safely aborts the programming operation and
resets the device to the Read mode.
Memory contents are not altered in an y c ase.
CE#
t
OEH
WE#
OE#
Data
DQ0–DQ7
DQ6 = DQ6 =
DQ6
Stop Toggling
DQ0–DQ7
Valid
t
OE
*
18879C-11
Note:
*DQ6 stops toggling (The device has completed the Embedded operation.)
Figure 6. AC Waveforms for Toggle Bit during Embedded Algor ith m Operati ons
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