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AM28F256A-120FC

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型号: AM28F256A-120FC
PDF文件:
  • AM28F256A-120FC PDF文件
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功能描述: 256 Kilobit (32 K x 8-Bit) CMOS 12.0 Volt, Bulk Erase Flash Memory with Embedded Algorithms
PDF文件大小: 456.67 Kbytes
PDF页数: 共35页
制造商: AMD[Advanced Micro Devices]
制造商LOGO: AMD[Advanced Micro Devices] LOGO
制造商网址: http://www.amd.com
捡单宝AM28F256A-120FC
PDF页面索引
120%
12 Am28F256A
FLASH MEMORY PROGRAM/ERASE
OPERATIONS
Embedded Erase Algorithm
The automatic chip erase does not require the device
to be entirely pre-programmed prior to executing the
Embedded set-up erase command and Embedded
erase command. Upon e x ec uting the Embedded er ase
command the device automatically will program and
verify the entire memory for an all zero data pattern.
The system is
not
required to provide any controls or
timing during these operations.
When the device is automatically verified to contain an
all zero pattern, a self-timed chip erase and verify be-
gin. The er ase and verify oper at ion are complete when
the data on DQ7 is “1" (see Write Operation Status sec-
tion) at which time the device returns to Read mode.
The system is not required to provide any control or
timing during these operations.
When using the E mbedd ed Erase algorithm, the erase
automatically terminates when adequate erase margin
has been achi eved for the memory arra y ( no erase v er-
ify command is required). The margin voltages are in-
ternally generated in the same manner as when the
standard erase verify command is used.
The Embedded Erase Set-Up command is a command
only operation that stages the device for automatic
electrical erasure of all bytes in the array. Embedded
Erase Setup is performed by writing 30h to the com-
mand register.
To commence automatic chip erase, t he command 30h
must be written again t o the command register . The au-
tomatic erase begins on the rising edge of the WE and
terminates when the data on DQ7 is “1" (see Write Op-
eration Status section) at which time the device ret urns
to Read mode.
Figure 1 and Tab l e 4 illustr ate t he Embedded Er ase al-
gorithm, a typical command string and bus operation.
Table 4. Embedded Erase Algorithm
Note: See AC and DC Characteristics for values of V
PP
parameters. The V
PP
power supply can be hard-wired to the device or
switchable. When V
PP
is switched, V
PPL
may be ground, no connect with a resistor tied to ground, or less than V
CC
+ 2 .0 V. Re f er
to Functional Description.
Bus Operations Command Comments
Standby Wait for V
PP
Ramp to V
PPH
(see Note)
Write
Embedded Erase Setup Command Data = 30h
Embedded Erase Command Data = 30h
Read Data
# Polling to Verify Erasure
Standby Compare Output to FFh
Read Available for Read Operations
START
Apply V
PPH
Erasure Completed
Data# Poll from Device
Write Embedded Erase Command
Write Embedded Erase Setup Command
18879C-6
Figure 1. Embedded Erase Algorithm
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