FINAL
Publicati on# 18879 Rev: C Amendment/+2
Issue Date: May 1998
Am28F256A
256 Kilobit (32 K x 8-Bit)
CMOS 12.0 Volt, Bulk Erase Flash Memory with Embedded Algorithms
DISTINCTIVE CHARACTERISTICS
■ High performan c e
— Access times as fast as 70 ns
■ CMOS low power consumption
— 30 mA maximum activ e current
— 100 µA maximum standb y current
— No data retention power consumption
■ Compatible with JEDEC-standard byte-wide
32-Pin EPROM pinouts
— 32-pin PDIP
— 32-pin PLCC
— 32-pin TSOP
■ 100,000 write/erase cycles minimum
■ Write and erase volta ge 12.0 V ±5%
■ Latch-up pr otected to 100 mA from –1 V to
V
CC
+1 V
■ Embedded Erase El ectrical Bulk Chip-Erase
— 1.5 seconds typical chip-erase including
pre-programming
■ Embedded
Program
— 14 µs typical byte-program including time-out
— 0.5 second typical chip program
■ Command register ar chitecture f o r
micr oprocessor/microcontroller compati b le
write interface
■ On-chip address and data latches
■ Advanced CMOS flash memory technol ogy
— Low cost single transist or memory cell
■ Embedded
algorithms for completely
self-timed write/erase operations
GENERAL DESCRIPTION
The Am28F256A is a 256 K Flash memor y organized
as 32 Kbytes of 8 bits each. AMD’s Flash memories
offer the most cost-effective and reliable read/write
non- v olatile random acces s memory. The Am28 F256A
is packaged in 32-pin PDIP, PLCC, and TSOP versions.
It is designed to be reprogrammed and erased in-sys-
tem or in standard EPROM programmers. The
Am28F256A is erased when shipped from the factory.
The standard Am28F256A offers access times as fast
as 70 ns, allowing operation of high-speed micropro-
cessors without wait states. To eliminate bus conten-
tion, the Am28F256A has separate chip enable (CE#)
and output enable (OE#) controls.
AMD’s Flash memories augment EPROM functionality
with in-circuit electrical erasure and prog ramming. The
Am28F256A uses a command register to manage this
functionality, while maintaining a standard JEDEC
Flash Standard 32-pin pinout. The command register
allows for 100% TTL level control inputs and fixed
pow er supply levels during erase and programming.
AMD’s Flash technology reliably stores memory con-
tents even after 100,000 erase and program cycles.
The AMD cell is designed to optimize the erase and
programming mechanisms. In addition, the combina-
tion of adv anced tunnel o xide processing and l ow inter-
nal electric fields for erase and programming
operations produces reliable cycling. The Am28F256A
uses a 12.0 V ± 5% V
PP
high voltage input to perform
the erase
and programming functions.
The highest degree of latch-up protection is achieved
with AMD’s proprietary non-epi process. Latch-up pro-
tection is provided for stresses up to 100 milliamps on
address and data pins from –1 V to V
CC
+1 V.
Embedded Program
The Am28F256A is byte programmable using the
Embedded Programming algorithm. The Embedded
Progr amming algorithm does not r equire t he system to
time-out or verify the data programmed. The typical
room temperature programming time of the
Am28F256A is one half second.
Embedded Erase
The entire chip is bulk erased using the Embedded
Erase algorithm. The Embedded
Erase algorithm
automatically programs the entire arra y prior to electrical
erase. The timing and verification of electrical erase are
