IGLOO nano Low Power Flash FPGAs
Revision 17 2-77
Timing Characteristics
1.5 V DC Core Voltage
Table 2-102 • RAM4K9
Commercial-Case Conditions: T
J
= 70°C, Worst-Case VCC = 1.425 V
Parameter Description Std. Units
t
AS
Address setup time 0.69 ns
t
AH
Address hold time 0.13 ns
t
ENS
REN, WEN setup time 0.68 ns
t
ENH
REN, WEN hold time 0.13 ns
t
BKS
BLK setup time 1.37 ns
t
BKH
BLK hold time 0.13 ns
t
DS
Input data (DIN) setup time 0.59 ns
t
DH
Input data (DIN) hold time 0.30 ns
t
CKQ1
Clock HIGH to new data valid on DOUT (output retained, WMODE = 0) 2.94 ns
Clock HIGH to new data valid on DOUT (flow-through, WMODE = 1) 2.55 ns
t
CKQ2
Clock HIGH to new data valid on DOUT (pipelined) 1.51 ns
t
C2CWWL
1
Address collision clk-to-clk delay for reliable write after write on same address; applicable
to closing edge
0.23 ns
t
C2CRWH
1
Address collision clk-to-clk delay for reliable read access after write on same address;
applicable to opening edge
0.35 ns
t
C2CWRH
1
Address collision clk-to-clk delay for reliable write access after read on same address;
applicable to opening edge
0.41 ns
t
RSTBQ
RESET Low to data out Low on DOUT (flow-through) 1.72 ns
RESET Low to data out Low on DOUT (pipelined) 1.72 ns
t
REMRSTB
RESET removal 0.51 ns
t
RECRSTB
RESET recovery 2.68 ns
t
MPWRSTB
RESET minimum pulse width 0.68 ns
t
CYC
Clock cycle time 6.24 ns
F
MAX
Maximum frequency 160 MHz
Notes:
1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-
Based cSoCs and FPGAs.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
