IGLOO nano Low Power Flash FPGAs
Revision 17 2-71
Table 2-101 • IGLOO nano CCC/PLL Specification
For IGLOO nano V2 Devices, 1.2 V DC Core Supply Voltage
Parameter Min. Typ. Max. Units
Clock Conditioning Circuitry Input Frequency f
IN_CCC
1.5 160 MHz
Clock Conditioning Circuitry Output Frequency f
OUT_CCC
0.75 160 MHz
Delay Increments in Programmable Delay Blocks
1, 2
580
3
ps
Number of Programmable Values in Each Programmable Delay Block 32
Serial Clock (SCLK) for Dynamic PLL
4,9
60
Input Cycle-to-Cycle Jitter (peak magnitude) 0.25 ns
Acquisition Time
LockControl = 0 300 µs
LockControl = 1 6.0 ms
Tracking Jitter
5
LockControl = 0 4 ns
LockControl = 1 3 ns
Output Duty Cycle 48.5 51.5 %
Delay Range in Block: Programmable Delay 1
1, 2
2.3 20.86 ns
Delay Range in Block: Programmable Delay 2
1, 2
0.025 20.86 ns
Delay Range in Block: Fixed Delay
1, 2
5.7 ns
VCO Output Peak-to-Peak Period Jitter F
CCC_OUT
6
Max Peak-to-Peak Period Jitter
6,7,8
SSO 2SSO 4 SSO 8SSO 16
0.75 MHz to 50MHz 0.50 1.20 2.00 3.00 %
50 MHz to 100 MHz 2.50 5.00 7.00 15.00 %
Notes:
1. This delay is a function of voltage and temperature. See Table 2-6 on page 2-6 and Table 2-7 on page 2-7 for deratings.
2. T
J
= 25°C, V
CC
= 1.2 V.
3. When the CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay
increments are available. Refer to the Libero SoC Online Help associated with the core for more information.
4. Maximum value obtained for a STD speed grade device in Worst-Case Commercial conditions. For specific junction
temperature and voltage supply levels, refer to Table 2-6 on page 2-6 and Table 2-7 on page 2-7 for derating values.
5. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock
edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter
parameter.
6. VCO output jitter is calculated as a percentage of the VCO frequency. The jitter (in ps) can be calculated by multiplying
the VCO period by the % jitter. The VCO jitter (in ps) applies to CCC_OUT, regardless of the output divider settings. For
example, if the jitter on VCO is 300 ps, the jitter on CCC_OUT is also 300 ps, no matter what the settings are for the
output divider.
7. Measurements done with LVTTL 3.3 V 8 mA I/O drive strength and high slew rate. VCC/VCCPLL = 1.14 V,
VCCI = 3.3 V, VQ/PQ/TQ type of packages, 20 pF load.
8. SSOs are outputs that are synchronous to a single clock domain and have their clock-to-out times within ±200 ps of
each other. Switching I/Os are placed outside of the PLL bank.
Refer to the "Simultaneously Switching Outputs (SSOs) and
Printed Circuit Board Layout" section in the IGLOO nano FPGA Fabric User’s Guide
.
9. The AGLN010, AGLN015, and AGLN020 devices do not support PLLs.
