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AGLN125V5-ZQNG81YI

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型号: AGLN125V5-ZQNG81YI
PDF文件:
  • AGLN125V5-ZQNG81YI PDF文件
  • AGLN125V5-ZQNG81YI PDF在线浏览
功能描述: IGLOO nano Low Power Flash FPGAs with Flash*Freeze Technology
PDF文件大小: 7699.28 Kbytes
PDF页数: 共150页
制造商: MICROSEMI[Microsemi Corporation]
制造商LOGO: MICROSEMI[Microsemi Corporation] LOGO
制造商网址: http://www.microsemi.com
捡单宝AGLN125V5-ZQNG81YI
PDF页面索引
120%
IGLOO nano DC and Switching Characteristics
2-64 Revision 17
Global Tree Timing Characteristics
Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not
include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be driven
and conditioned internally by the CCC module. For more details on clock conditioning capabilities, refer
to the "Clock Conditioning Circuits" section on page 2-70. Ta bl e 2 -8 8 to Table 2-96 on page 2-68 present
minimum and maximum global clock delays within each device. Minimum and maximum delays are
measured with minimum and maximum loading.
Timing Characteristics
1.5 V DC Core Voltage
Table 2-88 • AGLN010 Global Resource
Commercial-Case Conditions: T
J
= 70°C, VCC = 1.425 V
Parameter Description
Std.
UnitsMin.
1
Max.
2
t
RCKL
Input Low Delay for Global Clock 1.13 1.42 ns
t
RCKH
Input High Delay for Global Clock 1.15 1.50 ns
t
RCKMPWH
Minimum Pulse Width HIGH for Global Clock 1.40 ns
t
RCKMPWL
Minimum Pulse Width LOW for Global Clock 1.65 ns
t
RCKSW
Maximum Skew for Global Clock 0.35 ns
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-89 • AGLN015 Global Resource
Commercial-Case Conditions: T
J
= 70°C, VCC = 1.425 V
Parameter Description
Std.
UnitsMin.
1
Max.
2
t
RCKL
Input Low Delay for Global Clock 1.21 1.55 ns
t
RCKH
Input HIgh Delay for Global Clock 1.23 1.65 ns
t
RCKMPWH
Minimum Pulse Width HIGH for Global Clock 1.40 ns
t
RCKMPWL
Minimum Pulse Width LOW for Global Clock 1.65 ns
t
RCKSW
Maximum Skew for Global Clock 0.42 ns
Notes:
1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential element,
located in a lightly loaded row (single element is connected to the global net).
2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element, located in a fully
loaded row (all available flip-flops are connected to the global net in the row).
3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
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