IGLOO nano Low Power Flash FPGAs
Revision 17 2-61
Timing Characteristics
1.5 V DC Core Voltage
Figure 2-24 • Timing Model and Waveforms
PRE
CLR
Out
CLK
Data
EN
t
SUE
50%
50%
t
SUD
t
HD
50%
50%
t
CLKQ
0
t
HE
t
RECPRE
t
REMPRE
t
RECCLR
t
REMCLR
t
WCLR
t
WPRE
t
PRE2Q
t
CLR2Q
t
CKMPWH
t
CKMPWL
50% 50%
50%
50%
50%
50% 50%
50%
50%
50% 50%
50%
50%
50%
50%
Table 2-86 • Register Delays
Commercial-Case Conditions: T
J
= 70°C, Worst-Case VCC = 1.425 V
Parameter Description Std. Units
t
CLKQ
Clock-to-Q of the Core Register 0.89 ns
t
SUD
Data Setup Time for the Core Register 0.81 ns
t
HD
Data Hold Time for the Core Register 0.00 ns
t
SUE
Enable Setup Time for the Core Register 0.73 ns
t
HE
Enable Hold Time for the Core Register 0.00 ns
t
CLR2Q
Asynchronous Clear-to-Q of the Core Register 0.60 ns
t
PRE2Q
Asynchronous Preset-to-Q of the Core Register 0.62 ns
t
REMCLR
Asynchronous Clear Removal Time for the Core Register 0.00 ns
t
RECCLR
Asynchronous Clear Recovery Time for the Core Register 0.24 ns
t
REMPRE
Asynchronous Preset Removal Time for the Core Register 0.00 ns
t
RECPRE
Asynchronous Preset Recovery Time for the Core Register 0.23 ns
t
WCLR
Asynchronous Clear Minimum Pulse Width for the Core Register 0.30 ns
t
WPRE
Asynchronous Preset Minimum Pulse Width for the Core Register 0.30 ns
t
CKMPWH
Clock Minimum Pulse Width HIGH for the Core Register 0.56 ns
t
CKMPWL
Clock Minimum Pulse Width LOW for the Core Register 0.56 ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.