IGLOO nano DC and Switching Characteristics
2-56 Revision 17
1.2 V DC Core Voltage
Table 2-83 • Output DDR Propagation Delays
Commercial-Case Conditions: T
J
= 70°C, Worst-Case VCC = 1.14 V
Parameter Description Std. Units
t
DDROCLKQ
Clock-to-Out of DDR for Output DDR 1.60 ns
t
DDROSUD1
Data_F Data Setup for Output DDR 1.09 ns
t
DDROSUD2
Data_R Data Setup for Output DDR 1.16 ns
t
DDROHD1
Data_F Data Hold for Output DDR 0.00 ns
t
DDROHD2
Data_R Data Hold for Output DDR 0.00 ns
t
DDROCLR2Q
Asynchronous Clear-to-Out for Output DDR 1.99 ns
t
DDROREMCLR
Asynchronous Clear Removal Time for Output DDR 0.00 ns
t
DDRORECCLR
Asynchronous Clear Recovery Time for Output DDR 0.24 ns
t
DDROWCLR1
Asynchronous Clear Minimum Pulse Width for Output DDR 0.19 ns
t
DDROCKMPWH
Clock Minimum Pulse Width HIGH for the Output DDR 0.31 ns
t
DDROCKMPWL
Clock Minimum Pulse Width LOW for the Output DDR 0.28 ns
F
DDOMAX
Maximum Frequency for the Output DDR 160.00 MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.