IGLOO nano Low Power Flash FPGAs
Revision 17 2-55
Timing Characteristics
1.5 V DC Core Voltage
Figure 2-20 • Output DDR Timing Diagram
116
1
7
2
8
3
910
45
28 3 9
t
DDROREMCLR
t
DDROHD1
t
DDROREMCLR
t
DDROHD2
t
DDROSUD2
t
DDROCLKQ
t
DDRORECCLR
CLK
Data_R
Data_F
CLR
Out
t
DDROCLR2Q
7104
Table 2-82 • Output DDR Propagation Delays
Commercial-Case Conditions: T
J
= 70°C, Worst-Case VCC = 1.425 V
Parameter Description Std. Units
t
DDROCLKQ
Clock-to-Out of DDR for Output DDR 1.07 ns
t
DDROSUD1
Data_F Data Setup for Output DDR 0.67 ns
t
DDROSUD2
Data_R Data Setup for Output DDR 0.67 ns
t
DDROHD1
Data_F Data Hold for Output DDR 0.00 ns
t
DDROHD2
Data_R Data Hold for Output DDR 0.00 ns
t
DDROCLR2Q
Asynchronous Clear-to-Out for Output DDR 1.38 ns
t
DDROREMCLR
Asynchronous Clear Removal Time for Output DDR 0.00 ns
t
DDRORECCLR
Asynchronous Clear Recovery Time for Output DDR 0.23 ns
t
DDROWCLR1
Asynchronous Clear Minimum Pulse Width for Output DDR 0.19 ns
t
DDROCKMPWH
Clock Minimum Pulse Width HIGH for the Output DDR 0.31 ns
t
DDROCKMPWL
Clock Minimum Pulse Width LOW for the Output DDR 0.28 ns
F
DDOMAX
Maximum Frequency for the Output DDR 250.00 MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.