IGLOO nano DC and Switching Characteristics
2-54 Revision 17
Output DDR Module
Figure 2-19 • Output DDR Timing Model
Table 2-81 • Parameter Definitions
Parameter Name Parameter Definition Measuring Nodes (from, to)
t
DDROCLKQ
Clock-to-Out B, E
t
DDROCLR2Q
Asynchronous Clear-to-Out C, E
t
DDROREMCLR
Clear Removal C, B
t
DDRORECCLR
Clear Recovery C, B
t
DDROSUD1
Data Setup Data_F A, B
t
DDROSUD2
Data Setup Data_R D, B
t
DDROHD1
Data Hold Data_F A, B
t
DDROHD2
Data Hold Data_R D, B
Data_F
(from core)
CLK
CLKBUF
Out
FF2
INBUF
CLR
DDR_OUT
Output DDR
FF1
0
1
X
X
X
X
X
X
X
A
B
D
E
C
C
B
OUTBUF
Data_R
(from core)
