IGLOO nano DC and Switching Characteristics
2-50 Revision 17
1.2 V DC Core Voltage
Table 2-77 • Output Enable Register Propagation Delays
Commercial-Case Conditions: T
J
= 70°C, Worst-Case VCC = 1.14 V
Parameter Description Std. Units
t
OECLKQ
Clock-to-Q of the Output Enable Register 1.10 ns
t
OESUD
Data Setup Time for the Output Enable Register 1.15 ns
t
OEHD
Data Hold Time for the Output Enable Register 0.00 ns
t
OECLR2Q
Asynchronous Clear-to-Q of the Output Enable Register 1.65 ns
t
OEPRE2Q
Asynchronous Preset-to-Q of the Output Enable Register 1.65 ns
t
OEREMCLR
Asynchronous Clear Removal Time for the Output Enable Register 0.00 ns
t
OERECCLR
Asynchronous Clear Recovery Time for the Output Enable Register 0.24 ns
t
OEREMPRE
Asynchronous Preset Removal Time for the Output Enable Register 0.00 ns
t
OERECPRE
Asynchronous Preset Recovery Time for the Output Enable Register 0.24 ns
t
OEWCLR
Asynchronous Clear Minimum Pulse Width for the Output Enable Register 0.19 ns
t
OEWPRE
Asynchronous Preset Minimum Pulse Width for the Output Enable Register 0.19 ns
t
OECKMPWH
Clock Minimum Pulse Width HIGH for the Output Enable Register 0.31 ns
t
OECKMPWL
Clock Minimum Pulse Width LOW for the Output Enable Register 0.28 ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.