IGLOO nano Low Power Flash FPGAs
Revision 17 2-49
Output Enable Register
Timing Characteristics
1.5 V DC Core Voltage
Figure 2-16 • Output Enable Register Timing Diagram
50%
Preset
Clear
EOUT
CLK
D_Enable
50%
t
OESUD
t
OEHD
50% 50%
t
OECLKQ
1
0
t
OERECPRE
t
OEREMPRE
t
OERECCLR
t
OEREMCLR
t
OEWCLR
t
OEWPRE
t
OEPRE2Q
t
OECLR2Q
t
OECKMPWH
t
OECKMPWL
50% 50%
50% 50% 50%
50% 50%
50%
50%
50% 50%
50%
50%
50%
Table 2-76 • Output Enable Register Propagation Delays
Commercial-Case Conditions: T
J
= 70°C, Worst-Case VCC = 1.425 V
Parameter Description Std. Units
t
OECLKQ
Clock-to-Q of the Output Enable Register 0.75 ns
t
OESUD
Data Setup Time for the Output Enable Register 0.51 ns
t
OEHD
Data Hold Time for the Output Enable Register 0.00 ns
t
OECLR2Q
Asynchronous Clear-to-Q of the Output Enable Register 1.13 ns
t
OEPRE2Q
Asynchronous Preset-to-Q of the Output Enable Register 1.13 ns
t
OEREMCLR
Asynchronous Clear Removal Time for the Output Enable Register 0.00 ns
t
OERECCLR
Asynchronous Clear Recovery Time for the Output Enable Register 0.24 ns
t
OEREMPRE
Asynchronous Preset Removal Time for the Output Enable Register 0.00 ns
t
OERECPRE
Asynchronous Preset Recovery Time for the Output Enable Register 0.24 ns
t
OEWCLR
Asynchronous Clear Minimum Pulse Width for the Output Enable Register 0.19 ns
t
OEWPRE
Asynchronous Preset Minimum Pulse Width for the Output Enable Register 0.19 ns
t
OECKMPWH
Clock Minimum Pulse Width HIGH for the Output Enable Register 0.31 ns
t
OECKMPWL
Clock Minimum Pulse Width LOW for the Output Enable Register 0.28 ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
