IGLOO nano DC and Switching Characteristics
2-48 Revision 17
1.2 V DC Core Voltage
Table 2-75 • Output Data Register Propagation Delays
Commercial-Case Conditions: T
J
= 70°C, Worst-Case VCC = 1.14 V
Parameter Description Std. Units
t
OCLKQ
Clock-to-Q of the Output Data Register 1.52 ns
t
OSUD
Data Setup Time for the Output Data Register 1.15 ns
t
OHD
Data Hold Time for the Output Data Register 0.00 ns
t
OCLR2Q
Asynchronous Clear-to-Q of the Output Data Register 1.96 ns
t
OPRE2Q
Asynchronous Preset-to-Q of the Output Data Register 1.96 ns
t
OREMCLR
Asynchronous Clear Removal Time for the Output Data Register 0.00 ns
t
ORECCLR
Asynchronous Clear Recovery Time for the Output Data Register 0.24 ns
t
OREMPRE
Asynchronous Preset Removal Time for the Output Data Register 0.00 ns
t
ORECPRE
Asynchronous Preset Recovery Time for the Output Data Register 0.24 ns
t
OWCLR
Asynchronous Clear Minimum Pulse Width for the Output Data Register 0.19 ns
t
OWPRE
Asynchronous Preset Minimum Pulse Width for the Output Data Register 0.19 ns
t
OCKMPWH
Clock Minimum Pulse Width HIGH for the Output Data Register 0.31 ns
t
OCKMPWL
Clock Minimum Pulse Width LOW for the Output Data Register 0.28 ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.