IGLOO nano DC and Switching Characteristics
2-46 Revision 17
1.2 V DC Core Voltage
Table 2-73 • Input Data Register Propagation Delays
Commercial-Case Conditions: T
J
= 70°C, Worst-Case VCC = 1.14 V
Parameter Description Std. Units
t
ICLKQ
Clock-to-Q of the Input Data Register 0.68 ns
t
ISUD
Data Setup Time for the Input Data Register 0.97 ns
t
IHD
Data Hold Time for the Input Data Register 0.00 ns
t
ICLR2Q
Asynchronous Clear-to-Q of the Input Data Register 1.19 ns
t
IPRE2Q
Asynchronous Preset-to-Q of the Input Data Register 1.19 ns
t
IREMCLR
Asynchronous Clear Removal Time for the Input Data Register 0.00 ns
t
IRECCLR
Asynchronous Clear Recovery Time for the Input Data Register 0.24 ns
t
IREMPRE
Asynchronous Preset Removal Time for the Input Data Register 0.00 ns
t
IRECPRE
Asynchronous Preset Recovery Time for the Input Data Register 0.24 ns
t
IWCLR
Asynchronous Clear Minimum Pulse Width for the Input Data Register 0.19 ns
t
IWPRE
Asynchronous Preset Minimum Pulse Width for the Input Data Register 0.19 ns
t
ICKMPWH
Clock Minimum Pulse Width HIGH for the Input Data Register 0.31 ns
t
ICKMPWL
Clock Minimum Pulse Width LOW for the Input Data Register 0.28 ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-7 on page 2-7 for derating values.