IGLOO nano Low Power Flash FPGAs
Revision 17 2-45
Input Register
Timing Characteristics
1.5 V DC Core Voltage
Figure 2-14 • Input Register Timing Diagram
50%
Clear
Out_1
CLK
Data
Preset
50%
t
ISUD
t
IHD
50%
50%
t
ICLKQ
1
0
t
IRECPRE
t
IREMPRE
t
IRECCLR
t
IREMCLR
t
IWCLR
t
IWPRE
t
IPRE2Q
t
ICLR2Q
t
ICKMPWH
t
ICKMPWL
50%
50%
50%
50%
50%
50% 50%
50%
50%
50% 50%
50%
50%
50%
Table 2-72 • Input Data Register Propagation Delays
Commercial-Case Conditions: T
J
= 70°C, Worst-Case VCC = 1.425 V
Parameter Description Std. Units
t
ICLKQ
Clock-to-Q of the Input Data Register 0.42 ns
t
ISUD
Data Setup Time for the Input Data Register 0.47 ns
t
IHD
Data Hold Time for the Input Data Register 0.00 ns
t
ICLR2Q
Asynchronous Clear-to-Q of the Input Data Register 0.79 ns
t
IPRE2Q
Asynchronous Preset-to-Q of the Input Data Register 0.79 ns
t
IREMCLR
Asynchronous Clear Removal Time for the Input Data Register 0.00 ns
t
IRECCLR
Asynchronous Clear Recovery Time for the Input Data Register 0.24 ns
t
IREMPRE
Asynchronous Preset Removal Time for the Input Data Register 0.00 ns
t
IRECPRE
Asynchronous Preset Recovery Time for the Input Data Register 0.24 ns
t
IWCLR
Asynchronous Clear Minimum Pulse Width for the Input Data Register 0.19 ns
t
IWPRE
Asynchronous Preset Minimum Pulse Width for the Input Data Register 0.19 ns
t
ICKMPWH
Clock Minimum Pulse Width HIGH for the Input Data Register 0.31 ns
t
ICKMPWL
Clock Minimum Pulse Width LOW for the Input Data Register 0.28 ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.