IGLOO nano Low Power Flash FPGAs
Revision 17 2-43
Fully Registered I/O Buffers with Asynchronous Clear
Figure 2-13 • Timing Model of the Registered I/O Buffers with Asynchronous Clear
CLK
Pad Out
CLK
CLR
Data_out
Data
Y
AA
EOUT
DOUT
Core
Array
DQ
DFN1C1
CLR
DQ
DFN1C1
CLR
DQ
DFN1C1
CLR
D_Enable
CC
DD
EE
FF
LL
HH
JJ
CLKBUF
INBUF
TRIBUF
INBUF
CLKBUF
INBUF
Data Input I/O Register with
Active High Clear
Positive-Edge Triggered
Data Output Register and
Enable Output Register with
Active High Clear
Positive-Edge Triggered