IGLOO nano Low Power Flash FPGAs
Revision 17 2-37
1.5 V LVCMOS (JESD8-11)
Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general
purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer.
Table 2-57 • Minimum and Maximum DC Input and Output Levels
1.5 V
LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL
1
IIH
2
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
VmAmA
Max.
mA
3
Max.
mA
3
µA
4
µA
4
2 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 2 2 13 16 10 10
Notes:
1. I
IL
is the input leakage current per I/O pin over recommended operating conditions where –0.3 < VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions where VIH < VIN < VCCI. Input
current is larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Figure 2-10 • AC Loading
Table 2-58 • 1.5 V LVCMOS AC Waveforms, Measuring Points, and Capacitive Loads
Input LOW (V) Input HIGH (V) Measuring Point* (V) C
LOAD
(pF)
01.50.755
Note: *Measuring point = Vtrip. See Table 2-23 on page 2-20 for a complete table of trip points.
Test Point
Test Point
Enable Path
Datapath
5 pF
R = 1 k
R to VCCI for t
LZ
/ t
ZL
/ t
ZLS
R to GND for t
HZ
/ t
ZH
/ t
ZHS
5 pF for t
ZH
/ t
ZHS
/ t
ZL
/ t
ZLS
5 pF for t
HZ
/ t
LZ