IGLOO nano Low Power Flash FPGAs
Revision 17 2-33
Timing Characteristics
Applies to 1.5 V DC Core Voltage
Table 2-47 • 2.5 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: T
J
= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Drive Strength Speed Grade t
DOUT
t
DP
t
DIN
t
PY
t
PYS
t
EOUT
t
ZL
t
ZH
t
LZ
t
HZ
Units
2 mA STD 0.97 4.13 0.19 1.10 1.24 0.66 4.01 4.13 1.73 1.74 ns
4 mA STD 0.97 4.13 0.19 1.10 1.24 0.66 4.01 4.13 1.73 1.74 ns
8 mA STD 0.97 3.39 0.19 1.10 1.24 0.66 3.31 3.39 1.98 2.19 ns
8 mA STD 0.97 3.39 0.19 1.10 1.24 0.66 3.31 3.39 1.98 2.19 ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-48 • 2.5 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: T
J
= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V
Drive Strength Speed Grade t
DOUT
t
DP
t
DIN
t
PY
t
PYS
t
EOUT
t
ZL
t
ZH
t
LZ
t
HZ
Units
2 mA STD 0.97 2.19 0.19 1.10 1.24 0.66 2.23 2.11 1.72 1.80 ns
4 mA STD 0.97 2.19 0.19 1.10 1.24 0.66 2.23 2.11 1.72 1.80 ns
6 mA STD 0.97 1.81 0.19 1.10 1.24 0.66 1.85 1.63 1.97 2.26 ns
8 mA STD 0.97 1.81 0.19 1.10 1.24 0.66 1.85 1.63 1.97 2.26 ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.