IGLOO nano Low Power Flash FPGAs
Revision 17 2-29
3.3 V LVCMOS Wide Range
Table 2-40 • Minimum and Maximum DC Input and Output Levels for LVCMOS 3.3 V Wide Range
3.3 V LVCMOS
Wide Range
1
Equivalent
Software
Default
Drive
Strength
Option
4
VIL VIH VOL VOH IOL I
OH
IIL
2
IIH
3
Drive
Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
VµAµAµA
5
µA
5
100 µA 2 mA –0.3 0.8 2 3.6 0.2 VCCI – 0.2 100 100 10 10
100 µA 4 mA –0.3 0.8 2 3.6 0.2 VCCI – 0.2 100 100 10 10
100 µA 6 mA –0.3 0.8 2 3.6 0.2 VCCI – 0.2 100 100 10 10
100 µA 8mA –0.3 0.8 2 3.6 0.2 VCCI – 0.2 100 100 10 10
Notes:
1. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V Wide Range, as specified in the JEDEC JESD8-B
specification.
2. I
IL
is the input leakage current per I/O pin over recommended operating conditions where –0.3 < VIN < VIL.
3. I
IH
is the input leakage current per I/O pin over recommended operating conditions where VIH < VIN < VCCI. Input
current is larger when operating outside recommended ranges.
4. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive
strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models.
5. Currents are measured at 85°C junction temperature.
6. Software default selection is highlighted in gray.