IGLOO nano Low Power Flash FPGAs
Revision 17 2-27
Timing Characteristics
Applies to 1.5 V DC Core Voltage
Table 2-36 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: T
J
= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Drive Strength Speed Grade t
DOUT
t
DP
t
DIN
t
PY
t
PYS
t
EOUT
t
ZL
t
ZH
t
LZ
t
HZ
Units
2 mA STD 0.97 3.52 0.19 0.86 1.16 0.66 3.59 3.42 1.75 1.90 ns
4 mA STD 0.97 3.52 0.19 0.86 1.16 0.66 3.59 3.42 1.75 1.90 ns
6 mA STD 0.97 2.90 0.19 0.86 1.16 0.66 2.96 2.83 1.98 2.29 ns
8 mA STD 0.97 2.90 0.19 0.86 1.16 0.66 2.96 2.83 1.98 2.29 ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.
Table 2-37 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew – Applies to 1.5 V DC Core Voltage
Commercial-Case Conditions: T
J
= 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Drive Strength Speed Grade t
DOUT
t
DP
t
DIN
t
PY
t
PYS
t
EOUT
t
ZL
t
ZH
t
LZ
t
HZ
Units
2 mA STD 0.97 2.16 0.19 0.86 1.16 0.66 2.20 1.80 1.75 1.99 ns
4 mA STD 0.97 2.16 0.19 0.86 1.16 0.66 2.20 1.80 1.75 1.99 ns
6 mA STD 0.97 1.79 0.19 0.86 1.16 0.66 1.83 1.45 1.98 2.38 ns
8 mA STD 0.97 1.79 0.19 0.86 1.16 0.66 1.83 1.45 1.98 2.38 ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.