IGLOO nano Low Power Flash FPGAs
Revision 17 2-13
Combinatorial Cells Contribution—P
C-CELL
P
C-CELL
= N
C-CELL
*
1
/ 2 * PAC7 * F
CLK
N
C-CELL
is the number of VersaTiles used as combinatorial modules in the design.
1
is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-19 on
page 2-14.
F
CLK
is the global clock signal frequency.
Routing Net Contribution—P
NET
P
NET
= (N
S-CELL
+ N
C-CELL
) *
1
/ 2 * PAC8 * F
CLK
N
S-CELL
is the number of VersaTiles used as sequential modules in the design.
N
C-CELL
is the number of VersaTiles used as combinatorial modules in the design.
1
is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-19 on
page 2-14.
F
CLK
is the global clock signal frequency.
I/O Input Buffer Contribution—P
INPUTS
P
INPUTS
= N
INPUTS
*
2
/ 2 * PAC9 * F
CLK
N
INPUTS
is the number of I/O input buffers used in the design.
2
is the I/O buffer toggle rate—guidelines are provided in Table 2-19 on page 2-14.
F
CLK
is the global clock signal frequency.
I/O Output Buffer Contribution—P
OUTPUTS
P
OUTPUTS
= N
OUTPUTS
*
2
/ 2 *
1
* PAC10 * F
CLK
N
OUTPUTS
is the number of I/O output buffers used in the design.
2
is the I/O buffer toggle rate—guidelines are provided in Table 2-19 on page 2-14.
1
is the I/O buffer enable rate—guidelines are provided in Table 2-20 on page 2-14.
F
CLK
is the global clock signal frequency.
RAM Contribution—P
MEMORY
P
MEMORY
= PAC11 * N
BLOCKS
* F
READ-CLOCK
*
2
+ PAC12 * N
BLOCK
* F
WRITE-CLOCK
*
3
N
BLOCKS
is the number of RAM blocks used in the design.
F
READ-CLOCK
is the memory read clock frequency.
2
is the RAM enable rate for read operations.
F
WRITE-CLOCK
is the memory write clock frequency.
3
is the RAM enable rate for write operations—guidelines are provided in Table 2-20 on
page 2-14.
PLL Contribution—P
PLL
P
PLL
= PDC4 + PAC13 *F
CLKOUT
F
CLKOUT
is the output clock frequency.
1
1. If a PLL is used to generate more than one output clock, include each output clock in the formula by adding its corresponding
contribution (PAC13* FCLKOUT product) to the total PLL contribution.
