IGLOO nano DC and Switching Characteristics
2-12 Revision 17
Power Calculation Methodology
This section describes a simplified method to estimate power consumption of an application. For more
accurate and detailed power estimations, use the SmartPower tool in Libero SoC software.
The power calculation methodology described below uses the following variables:
• The number of PLLs as well as the number and the frequency of each output clock generated
• The number of combinatorial and sequential cells used in the design
• The internal clock frequencies
• The number and the standard of I/O pins used in the design
• The number of RAM blocks used in the design
• Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-19 on
page 2-14.
• Enable rates of output buffers—guidelines are provided for typical applications in Table 2-20 on
page 2-14.
• Read rate and write rate to the memory—guidelines are provided for typical applications in
Table 2-20 on page 2-14. The calculation should be repeated for each clock domain defined in the
design.
Methodology
Total Power Consumption—P
TOTAL
P
TOTAL
= P
STAT
+ P
DYN
P
STAT
is the total static power consumption.
P
DYN
is the total dynamic power consumption.
Total Static Power Consumption—P
STAT
P
STAT
= (PDC1 or PDC2 or PDC3) + N
BANKS
* PDC5
N
BANKS
is the number of I/O banks powered in the design.
Total Dynamic Power Consumption—P
DYN
P
DYN
= P
CLOCK
+ P
S-CELL
+ P
C-CELL
+ P
NET
+ P
INPUTS
+ P
OUTPUTS
+ P
MEMORY
+ P
PLL
Global Clock Contribution—P
CLOCK
P
CLOCK
= (PAC1 + N
SPINE
* PAC2 + N
ROW
* PAC3 + N
S-CELL
* PAC4) * F
CLK
N
SPINE
is the number of global spines used in the user design—guidelines are provided in
the "Spine Architecture" section of the IGLOO nano FPGA Fabric User's Guide
.
N
ROW
is the number of VersaTile rows used in the design—guidelines are provided in the
"Spine Architecture" section of the IGLOO nano FPGA Fabric User's Guide.
F
CLK
is the global clock signal frequency.
N
S-CELL
is the number of VersaTiles used as sequential modules in the design.
PAC1, PAC2, PAC3, and PAC4 are device-dependent.
Sequential Cells Contribution—P
S-CELL
P
S-CELL
= N
S-CELL
* (PAC5 +
1
/ 2 * PAC6) * F
CLK
N
S-CELL
is the number of VersaTiles used as sequential modules in the design. When a
multi-tile sequential cell is used, it should be accounted for as 1.
1
is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-19 on
page 2-14.
F
CLK
is the global clock signal frequency.
