IGLOO nano Low Power Flash FPGAs
Revision 17 2-9
Power per I/O Pin
Table 2-13 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings
Applicable to IGLOO nano I/O Banks
VCCI (V)
Dynamic Power
PAC9 (µW/MHz)
1
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS 3.3 16.38
3.3 V LVTTL / 3.3 V LVCMOS – Schmitt Trigger 3.3 18.89
3.3 V LVCMOS Wide Range
2
3.3 16.38
3.3 V LVCMOS Wide Range – Schmitt Trigger 3.3 18.89
2.5 V LVCMOS 2.5 4.71
2.5 V LVCMOS – Schmitt Trigger 2.5 6.13
1.8 V LVCMOS 1.8 1.64
1.8 V LVCMOS – Schmitt Trigger 1.8 1.79
1.5 V LVCMOS (JESD8-11) 1.5 0.97
1.5 V LVCMOS (JESD8-11) – Schmitt Trigger 1.5 0.96
1.2 V LVCMOS
3
1.2 0.57
1.2 V LVCMOS – Schmitt Trigger
3
1.2 0.52
1.2 V LVCMOS Wide Range
3
1.2 0.57
1.2 V LVCMOS Wide Range – Schmitt Trigger
3
1.2 0.52
Notes:
1. PAC9 is the total dynamic power measured on V
CCI
.
2. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.
3. Applicable to IGLOO nano V2 devices operating at VCCI VCC.
Table 2-14 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings
1
Applicable to IGLOO nano I/O Banks
C
LOAD
(pF) VCCI (V)
Dynamic Power
PAC10 (µW/MHz)
2
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS 5 3.3 107.98
3.3 V LVCMOS Wide Range
3
5 3.3 107.98
2.5 V LVCMOS 5 2.5 61.24
1.8 V LVCMOS 5 1.8 31.28
1.5 V LVCMOS (JESD8-11) 5 1.5 21.50
1.2 V LVCMOS
4
51.2 15.22
Notes:
1. Dynamic power consumption is given for standard load and software default drive strength and output slew.
2. PAC10 is the total dynamic power measured on VCCI.
3. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification.
4. Applicable for IGLOO nano V2 devices operating at VCCI VCC.
