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AGLN125V5-ZQNG81YI

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型号: AGLN125V5-ZQNG81YI
PDF文件:
  • AGLN125V5-ZQNG81YI PDF文件
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功能描述: IGLOO nano Low Power Flash FPGAs with Flash*Freeze Technology
PDF文件大小: 7699.28 Kbytes
PDF页数: 共150页
制造商: MICROSEMI[Microsemi Corporation]
制造商LOGO: MICROSEMI[Microsemi Corporation] LOGO
制造商网址: http://www.microsemi.com
捡单宝AGLN125V5-ZQNG81YI
PDF页面索引
120%
IGLOO nano DC and Switching Characteristics
2-6 Revision 17
Thermal Characteristics
Introduction
The temperature variable in the Microsemi Designer software refers to the junction temperature, not the
ambient temperature. This is an important distinction because dynamic and static power consumption
cause the chip junction temperature to be higher than the ambient temperature.
EQ 1 can be used to calculate junction temperature.
T
J
= Junction Temperature = T + T
A
EQ 1
where:
T
A
= Ambient temperature
T = Temperature gradient between junction (silicon) and ambient T =
ja
* P
ja
= Junction-to-ambient of the package.
ja
numbers are located in Figure 2-5.
P = Power dissipation
Package Thermal Characteristics
The device junction-to-case thermal resistivity is
jc
and the junction-to-ambient air thermal resistivity is
ja
. The thermal characteristics for
ja
are shown for two air flow rates. The maximum operating junction
temperature is 100°C. EQ 2 shows a sample calculation of the maximum operating power dissipation
allowed for a 484-pin FBGA package at commercial temperature and in still air.
EQ 2
Temperature and Voltage Derating Factors
Maximum Power Allowed
Max. junction temp. (C) Max. ambient temp. (C)
ja
(C/W)
------------------------------------------------------------------------------------------------------------------------------------------
100C70C
20.5°C/W
-------------------------------------
1.46 W===
Table 2-5 • Package Thermal Resistivities
Package Type
Pin
Count
jc
ja
UnitsStill Air
200 ft./
min.
500 ft./
min.
Chip Scale Package (CSP) 36 TBD TBD TBD TBD C/W
81 TBD TBD TBD TBD C/W
Quad Flat No Lead (QFN) 48 TBD TBD TBD TBD C/W
68 TBD TBD TBD TBD C/W
100 TBD TBD TBD TBD C/W
Very Thin Quad Flat Pack (VQFP) 100 10.0 35.3 29.4 27.1 C/W
Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays (normalized to T
J
= 70°C,
VCC = 1.425 V)
For IGLOO nano V2 or V5 Devices, 1.5 V DC Core Supply Voltage
Array Voltage
VCC (V)
Junction Temperature (°C)
–40°C –20°C 0°C 25°C 70°C 85°C 100°C
1.425 0.947 0.956 0.965 0.978 1.000 1.009 1.013
1.5 0.875 0.883 0.892 0.904 0.925 0.932 0.937
1.575 0.821 0.829 0.837 0.848 0.868 0.875 0.879
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