IGLOO nano Low Power Flash FPGAs
Revision 17 5-7
Revision 1 (cont’d) The "QN48" pin diagram was revised. 4-16
Packaging Advance
v0.2
Note 2 for the "QN48", "QN68", and "100-Pin QFN" pin diagrams was changed to
"The die attach paddle of the package is tied to ground (GND)."
4-16, 4-19
The "VQ100" pin diagram was revised to move the pin IDs to the upper left corner
instead of the upper right corner.
4-23
Revision 0 (Oct 2008)
Product Brief Advance
v0.2
The following tables and sections were updated to add the UC81 and CS81
packages for AGL030:
"IGLOO nano Devices"
"I/Os Per Package"
"IGLOO nano Products Available in the Z Feature Grade"
"Temperature Grade Offerings"
N/A
The "I/Os Per Package" table was updated to add the following information to
table note 4: "For nano devices, the VQ100 package is offered in both leaded and
RoHS-compliant versions. All other packages are RoHS-compliant only."
II
The "IGLOO nano Products Available in the Z Feature Grade" section was
updated to remove QN100 for AGLN250.
IV
The device architecture figures, Figure 1-3 • IGLOO Device Architecture Overview
with Two I/O Banks (AGLN060, AGLN125) through Figure 1-4 • IGLOO Device
Architecture Overview with Four I/O Banks (AGLN250), were revised. Figure 1-1 •
IGLOO Device Architecture Overview with Two I/O Banks and No RAM
(AGLN010 and AGLN030) is new.
1-4
through
1-5
The "PLL and CCC" section was revised to include information about CCC-GLs in
AGLN020 and smaller devices.
1-7
The "I/Os with Advanced I/O Standards" section was revised to add information
about IGLOO nano devices supporting double-data-rate applications.
1-8
Revision / Version Changes Page
