IGLOO nano Low Power Flash FPGAs
Revision 17 5-3
Revision 10
(Apr 2010)
References to differential inputs were removed from the datasheet, since IGLOO nano
devices do not support differential inputs (SAR 21449).
N/A
A parenthetical note, "hold previous I/O state in Flash*Freeze mode," was added to each
occurrence of bus hold in the datasheet (SAR 24079).
N/A
The "In-System Programming (ISP) and Security" section was revised to add 1.2 V
programming.
I
The note connected with the "IGLOO nano Ordering Information" table was revised to
clarify features not available for Z feature grade devices.
III
The "IGLOO nano Device Status" table is new. II
The definition of C in the "Temperature Grade Offerings" table was changed to "extended
commercial temperature range."
IV
1.2 V wide range was added to the list of voltage ranges in the "I/Os with Advanced I/O
Standards" section.
1-8
A note was added to Table 2-2 • Recommended Operating Conditions
1
regarding
switching from 1.2 V to 1.5 V core voltage for in-system programming. The VJTAG
voltage was changed from "1.425 to 3.6" to "1.4 to 3.6" (SAR 24052). The note regarding
voltage for programming V2 and V5 devices was revised (SAR 25213). The maximum
value for VPUMP programming voltage (operation mode) was changed from 3.45 V to
3.6 V (SAR 25220).
2-2
Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays (normalized to
TJ = 70°C, VCC = 1.425 V) and Table 2-7 • Temperature and Voltage Derating Factors
for Timing Delays (normalized to TJ = 70°C, VCC = 1.14 V) were updated. Table 2-8 •
Power Supply State per Mode is new.
2-6,
2-7
The tables in the "Quiescent Supply Current" section were updated (SAR 24882 and
SAR 24112).
2-7
VJTAG was removed from Table 2-10 • Quiescent Supply Current (IDD) Characteristics,
IGLOO nano Sleep Mode* (SARs 24112, 24882, and 79503).
2-8
The note stating what was included in I
DD
was removed from Table 2-11 • Quiescent
Supply Current (IDD) Characteristics, IGLOO nano Shutdown Mode. The note, "per
VCCI or VJTAG bank" was removed from Table 2-12 • Quiescent Supply Current (IDD),
No IGLOO nano Flash*Freeze Mode
1
. The note giving I
DD
was changed to "I
DD
=
N
BANKS
* I
CCI
+ I
CCA
."
2-8
The values in Table 2-13 • Summary of I/O Input Buffer Power (per pin) – Default I/O
Software Settings and Table 2-14 • Summary of I/O Output Buffer Power (per pin) –
Default I/O Software Settings
1
were updated. Wide range support information was
added.
2-9
Revision Changes Page
