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AGLN125V5-ZQNG81YI

AGLN125V5-ZQNG81YI首页预览图
型号: AGLN125V5-ZQNG81YI
PDF文件:
  • AGLN125V5-ZQNG81YI PDF文件
  • AGLN125V5-ZQNG81YI PDF在线浏览
功能描述: IGLOO nano Low Power Flash FPGAs with Flash*Freeze Technology
PDF文件大小: 7699.28 Kbytes
PDF页数: 共150页
制造商: MICROSEMI[Microsemi Corporation]
制造商LOGO: MICROSEMI[Microsemi Corporation] LOGO
制造商网址: http://www.microsemi.com
捡单宝AGLN125V5-ZQNG81YI
PDF页面索引
120%
Revision 17 5-1
5 – Datasheet Information
List of Changes
The following table lists critical changes that were made in each version of the IGLOO nano datasheet.
Revision Changes Page
Revision 17
(May 2013)
Deleted details related to Ambient temperature from "Enhanced Commercial
Temperature Range", "IGLOO nano Ordering Information", "Temperature Grade
Offerings", and Table 2-2 • Recommended Operating Conditions
1
to remove ambiguities
arising due to the same, and modified Note 2 (SAR 47063).
I, III, IV,
and 2-2
Revision 16
(December 2012)
The "IGLOO nano Ordering Information" section has been updated to mention "Y" as
"Blank" mentioning "Device Does Not Include License to Implement IP Based on the
Cryptography Research, Inc. (CRI) Patent Portfolio" (SAR 43174).
III
The note in Table 2-100 • IGLOO nano CCC/PLL Specification and Table 2-101 • IGLOO
nano CCC/PLL Specification referring the reader to SmartGen was revised to refer
instead to the online help associated with the core (SAR 42565).
2-70,
2-71
Live at Power-Up (LAPU) has been replaced with ’Instant On’. NA
Revision 15
(September 2012)
The status of the AGLN125 device has been modified from ’Advance’ to ’Production’ in
the "IGLOO nano Device Status" section (SAR 41416).
II
Libero Integrated Design Environment (IDE) was changed to Libero System-on-Chip
(SoC) throughout the document (SAR 40274).
NA
Revision 14
(September 2012)
The "Security" section was modified to clarify that Microsemi does not support read-back
of programmed data.
1-2
Revision 13
(June 2012)
Figure Figure 2-34 • FIFO Read and Figure 2-35 • FIFO Write have been added (SAR
34842).
2-82
The following sentence was removed from the "VMVx I/O Supply Voltage (quiet)" section
in the "Pin Descriptions" section: "Within the package, the VMV plane is decoupled from
the simultaneous switching noise originating from the output buffer VCCI domain" and
replaced with “Within the package, the VMV plane biases the input stage of the I/Os in
the I/O banks” (SAR 38319). The datasheet mentions that "VMV pins must be connected
to the corresponding VCCI pins" for an ESD enhancement.
3-1
Revision 12
(March 2012)
The "In-System Programming (ISP) and Security" section and "Security" section were
revised to clarify that although no existing security measures can give an absolute
guarantee, Microsemi FPGAs implement the best security available in the industry (SAR
34663).
I, 1-2
Notes indicating that AGLN015 is not recommended for new designs have been added
(SAR 35759).
Notes indicating that nano-Z devices are not recommended for new designs have been
added. The "Devices Not Recommended For New Designs" section is new (SAR
36759).
II, III
The Y security option and Licensed DPA Logo were added to the "IGLOO nano Ordering
Information" section. The trademarked Licensed DPA Logo identifies that a product is
covered by a DPA counter-measures license from Cryptography Research (SAR 34722).
III
The following sentence was removed from the "Advanced Architecture" section: "In
addition, extensive on-chip programming circuitry enables rapid, single-voltage (3.3 V)
programming of IGLOO nano devices via an IEEE 1532 JTAG interface" (SAR 34683).
1-3
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