IGLOO nano Low Power Flash FPGAs
Revision 17 1-5
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Figure 1-3 • IGLOO Device Architecture Overview with Two I/O Banks (AGLN060, AGLN125)
Figure 1-4 • IGLOO Device Architecture Overview with Four I/O Banks (AGLN250)
RAM Block
4,608-Bit Dual-Port
SRAM or FIFO Block
VersaTile
CCC
I/Os
ISP AES
Decryption
User Nonvolatile
FlashRom
Flash*Freeze
Technology
Charge
Pumps
Bank 0
Bank 1Bank 1
Bank 0Bank 0
Bank 1
RAM Block
4,608-Bit Dual-Port
SRAM or FIFO Block
VersaTile
CCC
I/Os
Bank 0
Bank 3Bank 3
Bank 1Bank 1
Bank 2
ISP AES
Decryption
User Nonvolatile
FlashRom
Flash*Freeze
Technology
Charge
Pumps