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AGLN125V5-ZQNG81YI

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型号: AGLN125V5-ZQNG81YI
PDF文件:
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功能描述: IGLOO nano Low Power Flash FPGAs with Flash*Freeze Technology
PDF文件大小: 7699.28 Kbytes
PDF页数: 共150页
制造商: MICROSEMI[Microsemi Corporation]
制造商LOGO: MICROSEMI[Microsemi Corporation] LOGO
制造商网址: http://www.microsemi.com
捡单宝AGLN125V5-ZQNG81YI
PDF页面索引
120%
IGLOO nano Low Power Flash FPGAs
Revision 17 3-3
should be treated as a sensitive asynchronous signal. When defining pin placement and board layout,
simultaneously switching outputs (SSOs) and their effects on sensitive asynchronous pins must be
considered.
Unused FF or I/O pins are tristated with weak pull-up. This default configuration applies to both
Flash*Freeze mode and normal operation mode. No user intervention is required.
Table 3-1 shows the Flash*Freeze pin location on the available packages for IGLOO nano devices. The
Flash*Freeze pin location is independent of device (except for a PQ208 package), allowing migration to
larger or smaller IGLOO nano devices while maintaining the same pin location on the board. Refer to the
"Flash*Freeze Technology and Low Power Modes" chapter of the IGLOO nano FPGA Fabric User’s
Guide for more information on I/O states during Flash*Freeze mode.
JTAG Pins
Low power flash devices have a separate bank for the dedicated JTAG pins. The JTAG pins can be run
at any voltage from 1.5 V to 3.3 V (nominal). VCC must also be powered for the JTAG state machine to
operate, even if the device is in bypass mode; VJTAG alone is insufficient. Both VJTAG and VCC to the
part must be supplied to allow JTAG signals to transition the device. Isolating the JTAG power supply in a
separate I/O bank gives greater flexibility in supply selection and simplifies power supply and PCB
design. If the JTAG interface is neither used nor planned for use, the VJTAG pin together with the TRST
pin could be tied to GND.
TCK Test Clock
Test clock input for JTAG boundary scan, ISP, and UJTAG. The TCK pin does not have an internal
pull-up/-down resistor. If JTAG is not used, Microsemi recommends tying off TCK to GND through a
resistor placed close to the FPGA pin. This prevents JTAG operation in case TMS enters an undesired
state.
Note that to operate at all VJTAG voltages, 500 to 1 k will satisfy the requirements. Refer to Table 3-2
for more information.
Table 3-1 • Flash*Freeze Pin Locations for IGLOO nano Devices
Package Flash*Freeze Pin
CS81/UC81 H2
QN48 14
QN68 18
VQ100 27
UC36 E2
Table 3-2 • Recommended Tie-Off Values for the TCK and TRST Pins
VJTAG Tie-Off Resistance
1,2
VJTAG at 3.3 V 200 to 1 k
VJTAG at 2.5 V 200 to 1 k
VJTAG at 1.8 V 500 to 1 k
VJTAG at 1.5 V 500 to 1 k
Notes:
1. The TCK pin can be pulled-up or pulled-down.
2. The TRST pin is pulled-down.
3. Equivalent parallel resistance if more than one device is on the JTAG chain
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