IGLOO nano Low Power Flash FPGAs
Revision 17 2-85
Timing Characteristics
1.5 V DC Core Voltage
Table 2-106 • FIFO
Worst Commercial-Case Conditions: T
J
= 70°C, VCC = 1.425 V
Parameter Description Std. Units
t
ENS
REN, WEN Setup Time 1.66 ns
t
ENH
REN, WEN Hold Time 0.13 ns
t
BKS
BLK Setup Time 0.30 ns
t
BKH
BLK Hold Time 0.00 ns
t
DS
Input Data (WD) Setup Time 0.63 ns
t
DH
Input Data (WD) Hold Time 0.20 ns
t
CKQ1
Clock High to New Data Valid on RD (flow-through) 2.77 ns
t
CKQ2
Clock High to New Data Valid on RD (pipelined) 1.50 ns
t
RCKEF
RCLK High to Empty Flag Valid 2.94 ns
t
WCKFF
WCLK High to Full Flag Valid 2.79 ns
t
CKAF
Clock High to Almost Empty/Full Flag Valid 10.71 ns
t
RSTFG
RESET Low to Empty/Full Flag Valid 2.90 ns
t
RSTAF
RESET Low to Almost Empty/Full Flag Valid 10.60 ns
t
RSTBQ
RESET Low to Data Out LOW on RD (flow-through) 1.68 ns
RESET Low to Data Out LOW on RD (pipelined) 1.68 ns
t
REMRSTB
RESET Removal 0.51 ns
t
RECRSTB
RESET Recovery 2.68 ns
t
MPWRSTB
RESET Minimum Pulse Width 0.68 ns
t
CYC
Clock Cycle Time 6.24 ns
F
MAX
Maximum Frequency for FIFO 160 MHz
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.