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AGLN125V5-ZQNG81YI

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型号: AGLN125V5-ZQNG81YI
PDF文件:
  • AGLN125V5-ZQNG81YI PDF在线浏览
功能描述: IGLOO nano Low Power Flash FPGAs with Flash*Freeze Technology
PDF文件大小: 7699.28 Kbytes
PDF页数: 共150页
制造商: MICROSEMI[Microsemi Corporation]
制造商LOGO: MICROSEMI[Microsemi Corporation] LOGO
制造商网址: http://www.microsemi.com
捡单宝
PDF页面索引
100%
June 2013 I
© 2013 Microsemi Corporation
IGLOO nano Low Power Flash FPGAs
with Flash*Freeze Technology
Features and Benefits
Low Power
nanoPower Consumption—Industry’s Lowest Power
1.2 V to 1.5 V Core Voltage Support for Low Power
Supports Single-Voltage System Operation
Low Power Active FPGA Operation
Flash*Freeze Technology Enables Ultra-Low Power
Consumption while Maintaining FPGA Content
Easy Entry to / Exit from Ultra-Low Power Flash*Freeze Mode
Small Footprint Packages
As Small as 3x3 mm in Size
Wide Range of Features
10,000 to 250,000 System Gates
Up to 36 kbits of True Dual-Port SRAM
Up to 71 User I/Os
Reprogrammable Flash Technology
130-nm, 7-Layer Metal, Flash-Based CMOS Process
Instant On Level 0 Support
Single-Chip Solution
Retains Programmed Design When Powered Off
250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System
Performance
In-System Programming (ISP) and Security
ISP Using On-Chip 128-Bit Advanced Encryption Standard
(AES) Decryption via JTAG (IEEE 1532–compliant)
FlashLock
®
Designed to Secure FPGA Contents
•1.2V Programming
High-Performance Routing Hierarchy
Segmented, Hierarchical Routing and Clock Structure
Advanced I/Os
1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation
Bank-Selectable I/O Voltages—up to 4 Banks per Chip
Single-Ended I/O Standards: LVTTL, LVCMOS
3.3V/2.5V/1.8V/1.5V/1.2V
Wide Range Power Supply Voltage Support per JESD8-B,
Allowing I/Os to Operate from 2.7 V to 3.6 V
Wide Range Power Supply Voltage Support per JESD8-12,
Allowing I/Os to Operate from 1.14 V to 1.575 V
I/O Registers on Input, Output, and Enable Paths
Selectable Schmitt Trigger Inputs
Hot-Swappable and Cold-Sparing I/Os
Programmable Output Slew Rate and Drive Strength
Weak Pull-Up/-Down
IEEE 1149.1 (JTAG) Boundary Scan Test
Pin-Compatible Packages across the IGLOO
®
Family
Clock Conditioning Circuit (CCC) and PLL
Up to Six CCC Blocks, One with an Integrated PLL
Configurable Phase Shift, Multiply/Divide, Delay
Capabilities, and External Feedback
Wide Input Frequency Range (1.5 MHz up to 250 MHz)
Embedded Memory
1 kbit of FlashROM User Nonvolatile Memory
SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM
Blocks (×1, ×2, ×4, ×9, and ×18 organizations)
True Dual-Port SRAM (except × 18 organization)
Enhanced Commercial Temperature Range
Tj = -20°C to +85°C
AGLN030 and smaller devices do not support this feature.
IGLOO nano Devices
AGLN010 AGLN015
1
AGLN020 AGLN060 AGLN125 AGLN250
IGLOO nano-Z Devices
1
AGLN030Z
1
AGLN060Z
1
AGLN125Z
1
AGLN250Z
1
System Gates 10,000 15,000 20,000 30,000 60,000 125,000 250,000
Typical Equivalent Macrocells 86 128 172 256 512 1,024 2,048
VersaTiles (D-flip-flops) 260 384 520 768 1,536 3,072 6,144
Flash*Freeze Mode (typical, µW) 2 4 4 5 10 16 24
RAM Kbits (1,024 bits)
2
18 36 36
4,608-Bit Blocks
2
––– 4 8 8
FlashROM Kbits (1,024 bits) 1 1 1 1 1 1 1
Secure (AES) ISP
2
––– YesYesYes
Integrated PLL in CCCs
2,3
––– 1 1 1
VersaNet Globals 4 4 4 6 18 18 18
I/O Banks 2 3 3 2 2 2 4
Maximum User I/Os (packaged device) 34 49 52 77 71 71 68
Maximum User I/Os (Known Good Die) 34 52 83 71 71 68
Package Pins
UC/CS
QFN
VQFP
UC36
QN48 QN68
UC81,
CS81
QN68
UC81, CS81
QN48, QN68
VQ100
CS81
VQ100
CS81
VQ100
CS81
VQ100
Notes:
1. Not recommended for new designs.
2. AGLN030 and smaller devices do not support this feature.
3. AGLN060, AGLN125, and AGLN250 in the CS81 package do not support PLLs.
4. For higher densities and support of additional features, refer to the IGLOO and IGLOOe datasheets.
Revision 17
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