Device Architecture
2-80 Revision 4
Figure 2-64 • Analog Block Macro
VAREF
ADCGNDREF
AV0
AC0
AT0
AV9
AC9
AT9
ATRETURN01
ATRETURN9
DENAV0
DENAC0
DAVOUT0
DACOUT0
DATOUT0
DACOUT9
DAVOUT9
DATOUT9
AG1
AG0
AG9
DENAT0
DENAV0
DENAC0
DENAT0
CMSTB0
CSMTB9
GDON0
GDON9
TMSTB0
TMSTB9
MODE[3:0]
TVC[7:0]
STC[7:0]
CHNUMBER[4:0]
TMSTINT
ADCSTART
VAREFSEL
PWRDWN
ADCRESET
BUSY
CALIBRATE
DATAVALID
SAMPLE
RESULT[11:0]
RTCMATCH
RTCXTLMODE
RTCXTLSEL
RTCPSMMATCH
RTCCLK
SYSCLK
ACMWEN ACMRDATA[7:0]
ACMRESET
ACMWDATA
ACMADDR
ACMCLK
AB