Device Architecture
2-68 Revision 4
Figure 2-54 • One Port Write / Other Port Read Same
Figure 2-55 • RAM Reset. Applicable to both RAM4K9 and RAM512x18.
A
0
A
2
A
3
A
0
A
1
A
4
CLK1
ADDR1
CLK2
ADDR2
DIN1
D
0
D
2
D
3
D
0
D
1
D
0
DOUT2
(flow-through)
DOUT2
(Pipelined)
t
CKQ2
t
CKQ1
t
WRO
t
AS
t
AH
t
DS
t
DH
t
AS
t
AH
D
n
D
n
CLK
RESET
DOUT|RD
D
n
t
CYC
t
CKH
t
CKL
t
RSTBQ
D
m