Fusion Family of Mixed Signal FPGAs
Revision 4 2-67
Figure 2-52 • RAM Write, Output Retained. Applicable to both RAM4K9 and RAM512x18.
Figure 2-53 • RAM Write, Output as Write Data (WMODE = 1). Applicable to RAM4K9 Only.
t
CYC
t
CKH
t
CKL
A
0
A
1
A
2
DI
0
DI
1
t
AS
t
AH
t
BKS
t
ENS
t
ENH
t
DS
t
DH
CLK
BLK
WEN
[R|W]ADDR
DIN|WD
D
n
DOUT|RD
t
BKH
D
2
t
CYC
t
CKH
t
CKL
A
0
A
1
A
2
t
AS
t
AH
t
BKS
t
ENS
t
DS
t
DH
CLK
BLK
WEN
ADDR
DIN
t
BKH
DOUT
(flow-through)
DOUT
(pipelined)
DI
0
DI
1
D
n
DI
0
DI
1
D
n
DI
1
DI
2
D
0