Fusion Device Family Overview
1-2 Revision 4
The on-chip crystal and RC oscillators work in conjunction with the integrated phase-locked loops (PLLs)
to provide clocking support to the FPGA array and on-chip resources. In addition to supporting typical
RTC uses such as watchdog timer, the Fusion RTC can control the on-chip voltage regulator to power
down the device (FPGA fabric, flash memory block, and ADC), enabling a low power standby mode.
The Fusion family offers revolutionary features, never before available in an FPGA. The nonvolatile flash
technology gives the Fusion solution the advantage of being a highly secure, low power, single-chip
solution that is Instant On. Fusion is reprogrammable and offers time-to-market benefits at an ASIC-level
unit cost. These features enable designers to create high-density systems using existing ASIC or FPGA
design flows and tools.
Flash Advantages
Reduced Cost of Ownership
Advantages to the designer extend beyond low unit cost, high performance, and ease of use. Flash-
based Fusion devices are Instant On and do not need to be loaded from an external boot PROM. On-
board security mechanisms prevent access to the programming information and enable remote updates
of the FPGA logic that are protected with high level security. Designers can perform remote in-system
reprogramming to support future design iterations and field upgrades, with confidence that valuable IP is
highly unlikely to be compromised or copied. ISP can be performed using the industry-standard AES
algorithm with MAC data authentication on the device. The Fusion family device architecture mitigates
the need for ASIC migration at higher user volumes. This makes the Fusion family a cost-effective ASIC
replacement solution for applications in the consumer, networking and communications, computing, and
avionics markets.
Security
As the nonvolatile, flash-based Fusion family requires no boot PROM, there is no vulnerable external
bitstream. Fusion devices incorporate FlashLock, which provides a unique combination of
reprogrammability and design security without external overhead, advantages that only an FPGA with
nonvolatile flash programming can offer.
Fusion devices utilize a 128-bit flash-based key lock and a separate AES key to provide the highest level
of protection in the FPGA industry for programmed IP and configuration data. The FlashROM data in
Fusion devices can also be encrypted prior to loading. Additionally, the flash memory blocks can be
programmed during runtime using the industry-leading AES-128 block cipher encryption standard (FIPS
Publication 192). The AES standard was adopted by the National Institute of Standards and Technology
(NIST) in 2000 and replaces the DES standard, which was adopted in 1977. Fusion devices have a built-
in AES decryption engine and a flash-based AES key that make Fusion devices the most comprehensive
programmable logic device security solution available today. Fusion devices with AES-based security
provide a high level of protection for remote field updates over public networks, such as the Internet, and
are designed to ensure that valuable IP remains out of the hands of system overbuilders, system cloners,
and IP thieves. As an additional security measure, the FPGA configuration data of a programmed Fusion
device cannot be read back, although secure design verification is possible. During design, the user
controls and defines both internal and external access to the flash memory blocks.
Security, built into the FPGA fabric, is an inherent component of the Fusion family. The flash cells are
located beneath seven metal layers, and many device design and layout techniques have been used to
make invasive attacks extremely difficult. Fusion with FlashLock and AES security is unique in being
highly resistant to both invasive and noninvasive attacks. Your valuable IP is protected with industry-
standard security, making remote ISP possible. A Fusion device provides the best available security for
programmable logic designs.
Single Chip
Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed, the
configuration data is an inherent part of the FPGA structure, and no external configuration data needs to
be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based Fusion FPGAs do
not require system configuration components such as EEPROMs or microcontrollers to load device
configuration data. This reduces bill-of-materials costs and PCB area, and increases security and system
reliability.
