Fusion Family of Mixed Signal FPGAs
Revision 4 2-59
Conversely, when writing 4-bit values and reading 9-bit values, the ninth bit of a read operation will be
undefined. The RAM blocks employ little-endian byte order for read and write operations.
Figure 2-47 • Fusion RAM Block with Embedded FIFO Controller
RCLK
WD
WCLK
Reset
RBLK
REN
ESTOP
WBLK
WEN
FSTOP
RD[17:0]
WD[17:0]
RCLK
WCLK
RADD[J:0]
WADD[J:0]
REN
FREN
FWEN
WEN
FULL
AEMPTY
AFULL
EMPTY
RD
RPIPE
RW[2:0]
WW[2:0]
RAM
CNT 12
E
=
E
=
AFVAL
AEVAL
SUB 12
CNT 12