Device Architecture
2-56 Revision 4
FlashROM
Fusion devices have 1 kbit of on-chip nonvolatile flash memory that can be read from the FPGA core
fabric. The FlashROM is arranged in eight banks of 128 bits during programming. The 128 bits in each
bank are addressable as 16 bytes during the read-back of the FlashROM from the FPGA core (Figure 2-
45).
The FlashROM can only be programmed via the IEEE 1532 JTAG port. It cannot be programmed directly
from the FPGA core. When programming, each of the eight 128-bit banks can be selectively
reprogrammed. The FlashROM can only be reprogrammed on a bank boundary. Programming involves
an automatic, on-chip bank erase prior to reprogramming the bank. The FlashROM supports a
synchronous read and can be read on byte boundaries. The upper three bits of the FlashROM address
from the FPGA core define the bank that is being accessed. The lower four bits of the FlashROM
address from the FPGA core define which of the 16 bytes in the bank is being accessed.
The maximum FlashROM access clock is given in Table 2-26 on page 2-57. Figure 2-46 shows the
timing behavior of the FlashROM access cycle—the address has to be set up on the rising edge of the
clock for DOUT to be valid on the next falling edge of the clock.
If the address is unchanged for two cycles:
• D0 becomes invalid t
CK2Q
ns after the second rising edge of the clock.
• D0 becomes valid again t
CK2Q
ns after the second falling edge.
If the address unchanged for three cycles:
• D0 becomes invalid t
CK2Q
ns after the second rising edge of the clock.
• D0 becomes valid again t
CK2Q
ns after the second falling edge.
• D0 becomes invalid t
CK2Q
ns after the third rising edge of the clock.
• D0 becomes valid again t
CK2Q
ns after the third falling edge.
Figure 2-45 • FlashROM Architecture
Bank Number
3 MSB of ADDR (READ)
Byte Number in Bank 4 LSB of ADDR (READ)
7
0
1
2
3
4
5
6
0123456789101112131415
